s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 151

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
FORMAT 1: MOVE SHIFTED REGISTER
OPERATION
These instructions move a shifted value between Lo registers. The THUMB assembler syntax is shown in
Table 4-2.
All instructions in this group set the CPSR condition codes.
OP
00
01
10
15
0
LSL Rd, Rs, #Offset5
LSR Rd, Rs, #Offset5
ASR Rd, Rs, #Offset5
14
0
THUMB Assembler
13
0
12
Table 4-2. Summary of Format 1 Instructions
Op
11
[2:0] Destination Register
[5:3] Source Register
[10:6] Immediate Vale
[12:11] Opcode
0 = LSL
1 = LSR
2 = ASR
10
MOVS Rd, Rs, LSL #Offset5
MOVS Rd, Rs, LSR #Offset5
MOVS Rd, Rs, ASR #Offset5 Perform arithmetic shift right on Rs
Figure 4-2. Format 1
ARM Equipment
Offset5
NOTE
6
5
Rs
Shift Rs left by a 5-bit immediate
value and store the result in Rd.
Perform logical shift right on Rs by a
5-bit immediate value and store the
result in Rd.
by a 5-bit immediate value and store
the result in Rd.
3
2
THUMB INSTRUCTION SET
Action
Rd
0
4-5