s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 230

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s3c2410a

Manufacturer Part Number
s3c2410a
Description
16/32-bit Risc Arm Microprocessor
Manufacturer
Samsung Semiconductor, Inc.
Datasheet

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CLOCK & POWER MANAGEMENT
Users can change the frequency by enabling SLOW mode bit in CLKSLOW register in PLL on state. The SLOW
clock is generated during the SLOW mode. Figure 7-9 shows the timing diagram.
If the user switches from SLOW mode to Normal mode by disabling the SLOW_BIT in the CLKSLOW register after
PLL lock time, the frequency is changed just after SLOW mode is disabled. Figure 7-10 shows the timing diagram.
7-12
Mpll
SLOW_BIT
MPLL_OFF
FCLK
Mpll
SLOW_BIT
MPLL_OFF
FCLK
Figure 7-10. Issuing Exit_from_Slow_mode Command After Lock Time
Figure 7-9. Issuing Exit_from_Slow_mode Command in PLL on State
Divided OSC clock
Slow mode enable
PLL off
Divided external clock
Slow mode enable
Slow mode disable
Software lock time
PLL on
It changes to PLL clock
after slow mode off
It changes to PLL clock
after slow mode off
Slow mode disable
S3C2410A

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