s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 79

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
Software Interrupt
The software interrupt instruction (SWI) is used for entering Supervisor mode, usually to request a particular
supervisor function. A SWI handler should return by executing the following irrespective of the state (ARM or Thumb):
This restores the PC and CPSR, and returns to the instruction following the SWI.
Undefined Instruction
When ARM920T comes across an instruction which it cannot handle, it takes the undefined instruction trap. This
mechanism may be used to extend either the THUMB or ARM instruction set by software emulation.
After emulating the failed instruction, the trap handler should execute the following irrespective of the state (ARM or
Thumb):
This restores the CPSR and returns to the instruction following the undefined instruction.
Exception Vectors
The following table shows the exception vector addresses.
nFIQ, nIRQ, ISYNC, LOCK, BIGEND, and ABORT pins exist only in the ARM920T CPU core.
0x0000000C
0x0000001C
0x00000000
0x00000004
0x00000008
0x00000010
0x00000014
0x00000018
Address
MOV
MOVS
PC,R14_svc
PC,R14_und
Reset
Undefined instruction
Software Interrupt
Abort (prefetch)
Abort (data)
Reserved
IRQ
FIQ
Table 2-3. Exception Vectors
Exception
NOTE
Supervisor
Undefined
Supervisor
Abort
Abort
Reserved
IRQ
FIQ
Mode in Entry
PROGRAMMER'S MODEL
2-13