s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 134

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s3c2410a

Manufacturer Part Number
s3c2410a
Description
16/32-bit Risc Arm Microprocessor
Manufacturer
Samsung Semiconductor, Inc.
Datasheet

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ARM INSTRUCTION SET
INSTRUCTION CYCLE TIMES
Coprocessor data operations take 1S + bI incremental cycles to execute, where b is the number of cycles spent in
the coprocessor busy-wait loop.
S and I are defined as sequential (S-cycle) and internal (I-cycle).
Assembler syntax
CDP{cond} p#,<expression1>,cd,cn,cm{,<expression2>}
{cond}
p#
<expression1>
cd, cn and cm
<expression2>
EXAMPLES
3-52
CDP
CDPEQ
Two character condition mnemonic. See Table 3-2.
The unique number of the required coprocessor
Evaluated to a constant and placed in the CP Opc field
Evaluate to the valid coprocessor register numbers CRd, CRn and CRm respectively
Where present is evaluated to a constant and placed in the CP field
p1,10,c1,c2,c3
p2,5,c1,c2,c3,2
; Request coproc 1 to do operation 10
; on CR2 and CR3, and put the result in CR1.
; If Z flag is set request coproc 2 to do operation 5 (type 2)
; on CR2 and CR3, and put the result in CR1.
S3C2410A

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