s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 464

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

IIC-BUS INTERFACE
MULTI-MASTER IIC-BUS CONTROL/STATUS (IICSTAT) REGISTER
20-12
IICSTAT
Mode selection
Busy signal status /
START STOP
condition
Serial output
Arbitration status
flag
Address-as-slave
status flag
Address zero status
flag
Last-received bit
status flag
Register
IICSTAT
0x54000004
Address
[7:6]
Bit
[5]
[4]
[3]
[2]
[1]
[0]
IIC-bus master/slave Tx/Rx mode select bits.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
IIC-Bus busy signal status bit.
0 = read) Not busy (when read)
1 = read) Busy (when read)
IIC-bus data output enable/disable bit.
0 = Disable Rx/Tx,
IIC-bus arbitration procedure status flag bit.
0 = Bus arbitration successful
1 = Bus arbitration failed during serial I/O
IIC-bus address-as-slave status flag bit.
0 = Cleared when START/STOP condition was
1 = Received slave address matches the address
IIC-bus address zero status flag bit.
0 = Cleared when START/STOP condition was
1 = Received slave address is 00000000b.
IIC-bus last-received bit status flag bit.
0 = Last-received bit is 0 (ACK was received).
1 = Last-received bit is 1 (ACK was not received).
write) STOP signal generation
write) START signal generation.
detected
value in the IICADD
detected.
R/W
R/W
The data in IICDS will be transferred
automatically just after the start signal.
IIC-Bus control/status register
1 = Enable Rx/Tx
Description
Description
Reset Value
Initial State
S3C2410A
0x0
00
0
0
0
0
0
0