s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 481

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
SPI SPECIAL REGISTERS
SPI CONTROL REGISTER
SPCON0
SPCON1
SPI Mode Select (SMOD)
SCK Enable (ENSCK)
Master/Slave Select
(MSTR)
Clock Polarity Select
(CPOL)
Clock Phase Select
(CPHA)
Tx Auto Garbage Data
mode enable (TAGD)
Register
SPCONn
0x59000000
0x59000020
Address
[6:5]
Bit
[4]
[3]
[2]
[1]
[0]
Determine how and by what SPTDAT is read/written.
00 = polling mode,
10 = DMA mode,
Determine whether you want SCK enable or not (for only
master).
0 = disable,
Determine the desired mode (master or slave).
0 = slave,
NOTE:
Determine an active high or active low clock.
0 = active high,
Select one of two fundamentally different transfer formats.
0 = format A,
Decide whether the receiving data only needs or not.
0 = normal mode,
NOTE:
R/W
R/W
R/W
In slave mode, there should be set up time for
In normal mode, if you only want to receive data,
master to initiate Tx/Rx.
you should transmit dummy 0xFF data.
SPI channel 0 control register
SPI channel 1 control register
Description
1 = Tx auto garbage data mode
1 = active low
1 = format B
11 = reserved
01 = interrupt mode
1 = enable
1 = master
Description
SPI INTERFACE
Reset Value
Initial State
0x00
0x00
00
0
0
0
0
0
22-7