s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 240

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

CLOCK & POWER MANAGEMENT
CLOCK SLOW CONTROL (CLKSLOW) REGISTER
CLOCK DIVIDER CONTROL (CLKDIVN) REGISTER
7-22
UCLK_ON
Reserved
MPLL_OFF
SLOW_BIT
Reserved
SLOW_VAL
HDIVN1
HDIVN
PDIVN
CLKSLOW
CLKSLOW
CLKDIVN
CLKDIVN
Register
Register
[2:0]
Bit
0x4C000010
0x4C000014
[2]
[1]
[0]
Bit
[7]
[6]
[5]
[4]
[3]
Address
Address
Special bus clock ratio available. (1:4:4)
0: Reserved
1: HCLK has the clock same as the FCLK/4.
PCLK has the clock same as the FCLK/4.
Note: If this bit is "0b1", HDIVN and PDIVN must be set "0b0".
0: HCLK has the clock same as the FCLK.
1: HCLK has the clock same as the FCLK/2.
0: PCLK has the clock same as the HCLK.
1: PCLK has the clock same as the HCLK/2.
0: UCLK ON (UPLL is also turned on and the UPLL lock time is
inserted automatically.)
1: UCLK OFF (UPLL is also turned off.)
Reserved
0 : PLL is turned on.
1 : PLL is turned off.
0 : FCLK = Mpll (MPLL output)
1: SLOW mode
The divider value for the slow clock when SLOW_BIT is on.
After PLL stabilization time (minimum 150us), SLOW_BIT
can be cleared to 0.
PLL is turned off only when SLOW_BIT is 1.
FCLK = input clock / (2 x SLOW_VAL) (SLOW_VAL > 0)
FCLK = input clock
input clock = XTIpll or EXTCLK
R/W
R/W
R/W
R/W
Description
Description
Clock divider control register
Slow clock control register
(SLOW_VAL = 0)
–
Description
Description
Reset Value
Reset Value
Initial State
Initial State
0x00000004
0x00000000
0x4
0
0
0
S3C2410A
0
–
0
0
–