s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 108

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

ARM INSTRUCTION SET
OPERAND RESTRICTIONS
CPSR FLAGS
Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N and Z flags are set
correctly on the result (N is equal to bit 63 of the result, Z is set if and only if all 64 bits of the result are zero). Both
the C and V flags are set to meaningless values.
INSTRUCTION CYCLE TIMES
MULL takes 1S + (m+1)I and MLAL 1S + (m+2)I cycles to execute, where m is the number of 8 bit multiplier array
cycles required to complete the multiply, which is controlled by the value of the multiplier operand specified by Rs.
Its possible values are as follows:
For Signed INSTRUCTIONS SMULL, SMLAL:
For Unsigned Instructions UMULL, UMLAL:
S and I are defined as sequential (S-cycle) and internal (I-cycle), respectively.
3-26
R15 must not be used as an operand or as a destination register.
RdHi, RdLo, and Rm must all specify different registers.
If bits [31:8] of the multiplier operand are all zero or all one.
If bits [31:16] of the multiplier operand are all zero or all one.
If bits [31:24] of the multiplier operand are all zero or all one.
In all other cases.
If bits [31:8] of the multiplier operand are all zero.
If bits [31:16] of the multiplier operand are all zero.
If bits [31:24] of the multiplier operand are all zero.
In all other cases.
S3C2410A