s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 553

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

ARM920T PROCESSOR
Appendix 3
MMU
ABOUT THE MMU
ARM920T implements an enhanced ARM Architecture V4 MMU to provide translation and access permission
checks for the instruction and data address ports of the ARM9TDMI. The MMU is controlled from a single set of two-
level page tables stored in main memory, and are enabled by M-Bit in CP15 register 1, providing a single address
translation and protection scheme. The instruction and data TLBs in the MMU can be independently locked and
flushed.
The MMU features are:
ACCESS PERMISSIONS AND DOMAINS
For large and small pages, access permissions are defined for each sub-page (1KB for small pages, 16KB for large
pages). Sections and tiny pages have a single set of access permissions.
All regions of memory have an associated domain. A domain is the primary access control mechanism for a region
of memory and defines the conditions in which an access can proceed. The domain determines whether:
the access permissions are used to qualify the access
the access is unconditionally allowed to proceed
the access is unconditionally aborted.
In the latter two cases, the access permission attributes are ignored.
There are 16 domains, which are configured using the domain access control register.
standard ARM V4 MMU mapping sizes, domains, and access protection scheme
mapping sizes are 1MB sections, 64KB large pages, 4KB small pages and new 1KB tiny pages
access permissions for sections
access permissions for large pages and small pages can be specified separately for each quarter of the page
(these quarters are called sub-pages)
16 domains implemented in hardware
64 entry instruction TLB and 64 entry data TLB
hardware page table walks
round-robin replacement algorithm (also called cyclic)
invalidate whole TLB via CP15 Register 8
invalidate TLB entry, selected by modified virtual address, via CP15 register 8
independent lockdown of instruction TLB and data TLB via CP15 register 10.
MMU
3-1