s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 315

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
UART FIFO CONTROL REGISTER
There are three UART FIFO control registers including UFCON0, UFCON1 and UFCON2 in the UART block.
NOTE:
Tx FIFO Trigger Level
Rx FIFO Trigger Level
Reserved
Tx FIFO Reset
Rx FIFO Reset
FIFO Enable
Register
UFCON0
UFCON1
UFCON2
When the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA receive
mode with FIFO, the Rx interrupt will be generated (receive time out), and the users should check the FIFO status
and read out the rest.
UFCONn
0x50000008
0x50004008
0x50008008
Address
[7:6]
[5:4]
Bit
[3]
[2]
[1]
[0]
Determine the trigger level of transmit FIFO.
00 = Empty
10 = 8-byte
Determine the trigger level of receive FIFO.
00 = 4-byte
10 = 12-byte
Auto-cleared after resetting FIFO
0 = Normal
Auto-cleared after resetting FIFO
0 = Normal
0 = Disable
R/W
R/W
R/W
R/W
UART channel 0 FIFO control register
UART channel 1 FIFO control register
UART channel 2 FIFO control register
Description
Description
11 = 16-byte
11 = 12-byte
01 = 8-byte
01 = 4-byte
1= Tx FIFO reset
1= Rx FIFO reset
1 = Enable
Reset Value
Initial State
0x0
0x0
0x0
00
00
0
0
0
0
11-13
UART