s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 225

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s3c2410a

Manufacturer Part Number
s3c2410a
Description
16/32-bit Risc Arm Microprocessor
Manufacturer
Samsung Semiconductor, Inc.
Datasheet

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S3C2410A
Change PLL Settings In Normal Operation Mode
During the operation of the S3C2410A in NORMAL mode, the user can change the frequency by writing the PMS
value and the PLL lock time will be automatically inserted. During the lock time, the clock is not supplied to the
internal blocks in the S3C2410A. Figure 7-5 shows the timing diagram.
USB Clock Control
USB host interface and USB device interface needs 48Mhz clock. In the S3C2410A, the USB dedicated PLL (UPLL)
generates 48MHz for USB. UCLK does not fed until the PLL (UPLL) is configured.
After reset
After configuring UPLL
UPLL is turned off by CLKSLOW register
UPLL is turned on by CLKSLOW register
Mpll
FCLK
Condition
Figure 7-5. Changing Slow Clock by Setting PMS Value
It changes to new PLL clock
after automatic lock time.
PMS setting
XTlpll or EXTCLK
L :
48MHz: after PLL lock time
XTlpll or EXTCLK
48MHz
PLL Lock-time
during PLL lock time
UCLK State
CLOCK & POWER MANAGEMENT
UPLL State
On
On
Off
On
7-7

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