s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 28

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

Table
Number
1-1
1-2
1-3
1-4
2-1
2-2
2-3
3-1
3-2
3-3
3-4
3-5
3-6
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
5-1
5-2
7-1
7-2
7-3
S3C2410A MICROPROCESSOR
272-Pin FBGA Pin Assignments – Pin Number Order .............................................1-7
272-Pin FBGA Pin Assignments...........................................................................1-10
S3C2410A Signal Descriptions .............................................................................1-20
S3C2410A Special Registers................................................................................1-26
PSR Mode Bit Values ..........................................................................................2-9
Exception Entry/Exit............................................................................................2-11
Exception Vectors ...............................................................................................2-13
The ARM Instruction Set ......................................................................................3-2
Condition Code Summary.....................................................................................3-4
ARM Data Processing Instructions........................................................................3-11
Incremental Cycle Times ......................................................................................3-16
Assembler Syntax Descriptions ............................................................................3-27
Addressing Mode Names .....................................................................................3-45
THUMB Instruction Set Opcodes ..........................................................................4-3
Summary of Format 1 Instructions ........................................................................4-5
Summary of Format 2 Instructions ........................................................................4-7
Summary of Format 3 Instructions ........................................................................4-9
Summary of Format 4 Instructions ........................................................................4-11
Summary of Format 5 Instructions ........................................................................4-13
Summary of PC-Relative Load Instruction ..............................................................4-16
Summary of Format 7 Instructions ........................................................................4-19
Summary of format 8 instructions..........................................................................4-20
Summary of Format 9 Instructions ........................................................................4-23
Halfword Data Transfer Instructions .......................................................................4-24
SP-Relative Load/Store Instructions ......................................................................4-26
Load Address......................................................................................................4-28
The ADD SP Instruction .......................................................................................4-30
PUSH and POP Instructions.................................................................................4-31
The Multiple Load/Store Instructions......................................................................4-33
The Conditional Branch Instructions ......................................................................4-34
The SWI Instruction .............................................................................................4-36
Summary of Branch Instruction.............................................................................4-37
The BL Instruction ...............................................................................................4-39
Bank 6/7 Addresses ............................................................................................5-2
SDRAM Bank Address Configuration.....................................................................5-4
Clock Source Selection at Boot-Up .......................................................................7-2
Clock and Power State in Each Power Mode .........................................................7-10
CLKSLOW and CLKDIVN Register Settings for SLOW Clock ..................................7-11
List of Tables
Title
Number
Page
xxvii