s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 336

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

USB DEVICE
END POINT0 CONTROL STATUS REGISTER (EP0_CSR)
This register has the control and status bits for Endpoint 0. Since a control transaction is involved with both IN and
OUT tokens, there is only one CSR register, mapped to the IN CSR1 register. (share IN1_CSR and can access by
writing index register "0" and read/write IN1_CSR)
13-12
EP0_CSR
SERVICED_SETUP_E
ND
SERVICED_OUT_
PKT_RDY
SEND_STALL
SETUP_END
DATA_END
SENT_STALL
EP0_CSR
Register
0x52000187(B)
0x52000184(L)
Bit
[7]
[6]
[5]
[4]
[3]
[2]
Address
CLEAR
MCU
R/W
SET
W
W
R
CLEAR
CLEAR
CLEAR
CLEAR
(byte)
R/W
R/W
USB
SET
SET
Endpoint 0 status register
The MCU should write a "1" to this bit to
clear SETUP_END.
The MCU should write a "1" to this bit to
clear OUT_PKT_RDY.
MCU should write a "1" to this bit at the
same time it clears OUT_PKT_RDY, if it
decodes an invalid token.
0 = Finish the STALL condition
1 = The USB issues a STALL and shake to
the current control transfer.
Set by the USB when a control transfer
ends before DATA_END is set.
When the USB sets this bit, an interrupt is
generated to the MCU.
When such a condition occurs, the USB
flushes the FIFO and invalidates MCU
access to the FIFO.
Set by the MCU on the conditions below:
1. After loading the last packet of data into
the FIFO, at the same time IN_PKT_RDY is
set.
2. While it clears OUT_PKT_RDY after
unloading the last packet of data.
3. For a zero length data phase.
Set by the USB if a control transaction is
stopped due to a protocol violation. An
interrupt is generated when this bit is set.
The MCU should write "0" to clear this bit.
Description
Description
Reset Value
Initial State
S3C2410A
0x00
0
0
0
0
0
0