s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 338

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

USB DEVICE
END POINT IN CONTROL STATUS REGISTER (IN_CSR1_REG/IN_CSR2_REG)
13-14
IN_CSR1_REG
Reserved
CLR_DATA_
TOGGLE
SENT_STALL
SEND_STALL
FIFO_FLUSH
Reserved
IN_CSR1_REG
Register
[2:1]
0x52000187(B)
0x52000184(L)
Bit
[7]
[6]
[5]
[4]
[3]
Address
CLEAR
MCU
R/W
W/R
R/W
R/
–
–
CLEAR
CLEAR
(byte)
R/W
R/W
USB
SET
R/
R
–
–
IN END POINT control status register1
Used in Set-up procedure.
0: There are alternation of DATA0 and DATA1
1: The data toggle bit is cleared and PID in
packet will maintain DATA0
Set by the USB when an IN token issues a
STALL handshake, after the MCU sets
SEND_STALL bit to start STALL handshaking.
When the USB issues a STALL handshake,
IN_PKT_RDY is cleared
0: The MCU clears this bit to finish the
STALL condition.
1: The MCU issues a STALL handshake to
the USB.
Set by the MCU if it intends to flush the
packet in Input-related FIFO. This bit is
cleared by the USB when the FIFO is flushed.
The MCU is interrupted when this happens. If
a token is in process, the USB waits until the
transmission is complete before FIFO flushing.
If two packets are loaded into the FIFO, only
first packet (The packet is intended to be sent
to the host) is flushed, and the corresponding
IN_PKT_RDY bit is cleared
Description
Description
–
–
Reset Value
Initial State
S3C2410A
0x00
0
0
0
0
0
0