s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 243

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
EXTERNAL DMA DREQ/DACK PROTOCOL
There are three types of external DMA request/acknowledge protocols (Single service Demand, Single service
Handshake and Whole service Handshake mode). Each type defines how the signals like DMA request and
acknowledge are related to these protocols.
Basic DMA Timing
The DMA service means performing paired Reads and Writes cycles during DMA operation, which can make one
DMA operation. Figure 8-1 shows the basic Timing in the DMA operation of the S3C2410A.
— The setup time and the delay time of XnXDREQ and XnXDACK are the same in all the modes.
— If the completion of XnXDREQ meets its setup time, it is synchronized twice and then XnXDACK is asserted.
— After assertion of XnXDACK, DMA requests the bus and if it gets the bus it performs its operations. XnXDACK is
(V
eXternal Request Setup
aCcess to Ack Delay when Low transition
aCcess to Ack Delay when High transition
DD
deasserted when DMA operation is completed.
XSCLK
XnXDREQ
XnXDACK
= 1.8 V
0.15 V/2.0V
Parameter
Table 8-2. DMA Controller Module Signal Timing Constants
2 SCLK
tXRS
0.1V, T
tCADL
Figure 8-1. Basic DMA Timing Diagram
A
= -40 to 85 C, V
Min. 3 SCLK
Symbol
t
t
EXT
t
CADL
CADH
XRS
= 3.3V
Read
tXRS
Min
0.3V)
Write
2
9
9
tCADH
Typ.
–
–
–
11 / 10
11 / 10
Max
6 / 5
Unit
ns
ns
ns
DMA
8-3