s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 204

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

MEMORY CONTROLLER
BUS WIDTH & WAIT CONTROL REGISTER (BWSCON) (Continued)
NOTES:
1.
2.
5-14
clock. In this chapter (Memory Controller), one clock means one bus clock.
All types of master clock in this memory controller correspond to the bus clock.
For example, HCLK in SRAM is the same as the bus clock, and SCLK in SDRAM is also the same as the bus
nBE[3:0] is the 'AND' signal nWBE[3:0] and nOE.
BWSCON
Reserved
WS2
DW2
WS1
DW1
DW0
ST1
[9:8]
[5:4]
[2:1]
[10]
Bit
[7]
[6]
[0]
Determine WAIT status for bank 2.
0 = WAIT disable
Determine data bus width for bank 2.
00 = 8-bit
Determine SRAM for using UB/LB for bank 1.
0 = Not using UB/LB (The pins are dedicated nWBE[3:0])
1 = Using UB/LB (The pins are dedicated nBE[3:0])
Determine WAIT status for bank 1.
0 = WAIT disable,
Determine data bus width for bank 1.
00 = 8-bit
Indicate data bus width for bank 0 (read only).
01 = 16-bit,
The states are selected by OM[1:0] pins
01 = 16-bit,
01 = 16-bit,
10 = 32-bit
1 = WAIT enable
1 = WAIT enable
Description
10 = 32-bit
10 = 32-bit
11 = reserved
11 = reserved
Initial state
S3C2410A
0
0
0
0
0
-
-