s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 132

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

ARM INSTRUCTION SET
ASSEMBLER SYNTAX
SWI{cond} <expression>
{cond}
<expression>
Examples
Supervisor code
The previous examples assume that suitable supervisor code exists, for instance:
ReadC
WriteI
3-50
SWI
SWI
SWINE
0x08 B Supervisor
EntryTable
DCD ZeroRtn
DCD ReadCRtn
DCD WriteIRtn
Zero
EQU 256
EQU 512
Supervisor
STMFD
LDR
BIC
MOV
ADR
LDR
WriteIRtn
LDMFD
Two character condition mnemonic, Table 3-2.
Evaluated and placed in the comment field (which is ignored by ARM920T).
ReadC
WriteI+"k”
0
EQU 0
R13,{R0-R2,R14}
R0,[R14,#-4]
R0,R0,#0xFF000000
R1,R0,LSR#8
R2,EntryTable
R15,[R2,R1,LSL#2]
R13,{R0-R2,R15}^
; Get next character from read stream.
; Output a "k" to the write stream.
; Conditionally call supervisor with 0 in comment field.
; SWI entry point
; Addresses of supervisor routines
; SWI has routine required in bits 8-23 and data (if any) in
; bits 0-7. Assumes R13_svc points to a suitable stack
; Save work registers and return address.
; Get SWI instruction.
; Clear top 8 bits.
; Get routine offset.
; Get start address of entry table.
; Branch to appropriate routine.
; Enter with character in R0 bits 0-7.
; Restore workspace and return,
; restoring processor mode and flags.
S3C2410A