s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 407

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
Gray Level Selection Guide
The S3C2410A LCD controller can generate 16 gray level using Frame Rate Control (FRC). The FRC characteristics
may cause unexpected patterns in gray level. These unwanted erroneous patterns may be shown in fast response
LCD or at lower frame rates.
Because the quality of LCD gray levels depends on LCD's own characteristics, the user has to select an appropriate
gray level after viewing all gray levels on user's own LCD.
Select the gray level quality through the following procedures:
1. Get the latest dithering pattern register value from SAMSUNG.
2. Display 16 gray bar in LCD.
3. Change the frame rate into an optimal value.
4. Change the VM alternating period to get the best quality.
5. As viewing 16 gray bars, select a good gray level, which is displayed well on your LCD.
6. Use only the good gray levels for quality.
LCD Refresh Bus Bandwidth Calculation Guide
The S3C2410A LCD controller can support various LCD display sizes. To select a suitable size (for the flicker free
LCD system application), the user have to consider the LCD refresh bus bandwidth determined by the LCD display
size, bit per pixel (bpp), frame rate, memory bus width, memory type, and so on.
Pdma means LCD DMA access period. In other words, the value of Pdma indicates the period of four-beat burst (4-
words burst) for video data fetch. So, Pdma depends on memory type and memory setting.
Eventually, LCD System Load is determined by LCD DMA Burst Count and Pdma.
Example 3:
640
frequency is 60 MHz
LCD Data Rate = 8
LCD DMA Burst Count = 18.432 / 16 = 1.152M/s
Pdma = (Trp+Trcd+CL+(2
LCD System Load = 1.152
System Bus Occupation Rate = (0.288/1)
LCD Data Rate (Byte/s) = bpp x (Horizontal display size) x (Vertical display size) x (Frame rate) /8
LCD DMA Burst Count (Times/s) = LCD Data Rate(Byte/s) /16(Byte) ; LCD DMA using 4words(16Byte) burst
LCD System Load = LCD DMA Burst Count x Pdma
480, 8bpp, 60 frame/sec, 16-bit data bus width, SDRAM (Trp=2HCLK / Trcd=2HCLK / CL=2HCLK) and HCLK
640
480
4)+1)
250 = 0.288
60 / 8 = 18.432Mbyte/s
(1/60 MHz) = 0.250ms
100 = 28.8%
LCD CONTROLLER
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