s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 99

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
ASSEMBLER SYNTAX
where:
<Op2>
{cond}
{S}
Rd, Rn and Rm Expressions evaluating to a register number.
<#expression>
<shift>
<shiftname>s
EXAMPLES
MOV,MVN (single operand instructions).
<opcode>{cond}{S} Rd,<Op2>
CMP,CMN,TEQ,TST (instructions which do not produce a result).
<opcode>{cond} Rn,<Op2>
AND,EOR,SUB,RSB,ADD,ADC,SBC,RSC,ORR,BIC
<opcode>{cond}{S} Rd,Rn,<Op2>
ADDEQ
TEQS
SUB
MOV
MOVS
Rm{,<shift>} or,<#expression>
A two-character condition mnemonic. See Table 3-2.
Set condition codes if S present (implied for CMP, CMN, TEQ, TST).
If this is used, the assembler will attempt to generate a shifted immediate 8-bit field to
match the expression. If this is impossible, it will give an error.
<Shiftname> <register> or <shiftname> #expression, or RRX (rotate right one bit with
extend).
ASL, LSL, LSR, ASR, ROR. (ASL is a synonym for LSL, they assemble to the same
code.)
R2,R4,R5
R4,#3
R4,R5,R7,LSR R2
PC,R14
PC,R14
; If the Z flag is set make R2:=R4+R5
; Test R4 for equality with 3.
; (The S is in fact redundant as the
; assembler inserts it automatically.)
; Logical right shift R7 by the number in
; the bottom byte of R2, subtract result
; from R5, and put the answer into R4.
; Return from subroutine.
; Return from exception and restore CPSR
; from SPSR_mode.
ARM INSTRUCTION SET
3-17