s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 581

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

ARM920T PROCESSOR
INSTRUCTION CACHE ENABLE/DISABLE
On reset, the ICache entries are all invalidated and the ICache is disabled.
The ICache is enabled by writing 1 to the Icr bit, and disabled by writing 0 to the Icr bit.
The ICache is usually used with the MMU enabled, in which case the C bit in the relevant MMU translation table
descriptor indicates whether an area of memory is cacheable. If the ICache is enabled with the MMU disabled, all
instruction fetches are treated as cacheable.
When the ICache is disabled, the cache contents are ignored and all instruction fetches appear on the ASB as
separate non-sequential accesses.
If the cache is subsequently re-enabled its contents will be unchanged. If the contents are no longer coherent with
main memory the ICache should be invalidated prior to being enabled (see Register 7: Cache operations on
page 2-15).
The MMU and ICache can be enabled simultaneously by writing a 1 to bit 0 and to bit 12 in CP15 register 1 with a
single MCR instruction.
INSTRUCTION CACHE OPERATION
If the ICache is disabled, each instruction fetch results in a separate non-sequential memory access on the ASB,
giving very low performance to burst memory such as page mode DRAM or synchronous DRAM. Therefore, the
ICache should be enabled as soon as possible after reset.
If the ICache is enabled, an ICache lookup is performed for each instruction fetch regardless of the setting of the Ctt
bit in the relevant MMU translation table descriptor. If the required instruction is found in the cache, the lookup is
called a cache hit. If the required instruction is not found in the cache, the lookup is called a cache miss.
If the instruction fetch is a cache hit and Ctt = 1 indicating a cacheable region of memory, then the instruction is
returned from the cache to the ARM9TDMI CPU core. If it is a cache miss and Ctt = 1, then an 8-word linefill will be
performed, possibly replacing another entry. The entry to be replaced, (called the victim), is chosen from the entries
which are not locked using either a random or round-robin replacement policy.
If Ctt = 0, indicating a non-cacheable region of memory, then a single non-sequential memory access will appear on
the ASB.
ARM920T implements a non-sequential access on the ASB as an A-TRAN cycle followed by an S-TRAN
cycle. It does not produce N-TRAN cycles.
If Ctt=0, indicating a non-cacheable region of memory, then the cache lookup should result in a cache miss.
The only way that it can result in a cache hit is if software has changed the value of the Ctt bit in the MMU
translation table descriptor without invalidating the cache contents. This is a programming error, as the
behavior in this case is architecturally unpredictable and varies between implementations.
NOTE
NOTE
CACHES, WRITE BUFFER
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