s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 86

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

ARM INSTRUCTION SET
THE CONDITION FIELD
In ARM state, all instructions are conditionally executed according to the state of the CPSR condition codes and the
instruction's condition field. This field (bits 31:28) determines the circumstances under which an instruction is to be
executed. If the state of the C, N, Z and V flags fulfils the conditions encoded by the field, the instruction is
executed, otherwise it is ignored.
There are sixteen possible conditions, each represented by a two-character suffix that can be appended to the
instruction's mnemonic. For example, a Branch (B in assembly language) becomes BEQ for "Branch if Equal", which
means the Branch will only be taken if the Z flag is set.
In practice, fifteen different conditions may be used: these are listed in Table 3-2. The sixteenth (1111) is reserved,
and must not be used.
In the absence of a suffix, the condition field of most instructions is set to "Always" (suffix AL). This means the
instruction will always be executed regardless of the CPSR condition codes.
3-4
Code
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
Suffix
EQ
NE
CS
CC
VS
VC
GE
PL
LS
GT
LE
AL
MI
LT
HI
Table 3-2. Condition Code Summary
Z set
Z clear
C set
C clear
N set
N clear
V set
V clear
C set and Z clear
C clear or Z set
N equals V
N not equal to V
Z clear AND (N equals V)
Z set OR (N not equal to V)
(ignored)
Flags
equal
not equal
unsigned higher or same
unsigned lower
negative
positive or zero
overflow
no overflow
unsigned higher
unsigned lower or same
greater or equal
less than
greater than
less than or equal
always
Meaning
S3C2410A