s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 536

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

PROGRAMMER'S MODEL
REGISTER 0: CACHE TYPE REGISTER
This is a read-only register which contains information about the size and architecture of the caches, allowing
operating systems to establish how to perform such operations as cache cleaning and lockdown. Future ARM
cached processors will contain this register, allowing RTOS vendors to produce future-proof versions of their
operating systems.
The cache type register is accessed by reading CP15 register 0 with the opcode_2 field set to 1. For example:
MRC p15,0,Rd,c0,c0,1; returns cache details
The format of the register is shown in Table 2-6.
Bits [28:25] indicate which major cache class the implementation falls into. 0x6 means that the cache provides:
2-8
Cache-clean-step operation
Cache-flush-step operation
Lock down facilities
Register Bits
31:29
28:25
23:21
20:18
17:15
13:12
11:9
8:6
5:3
1:0
24
14
2
Table 2-6. Cache Type Register Format
DCache words per line
ICache words per line
DCache associativity
ICache Associativity
Harvard/Unified
DCache size
ICache size
Cache type
Function
Reserved
Reserved
Reserved
Reserved
Reserved
10 (defines 8 words per line)
10 (defines 8 words per line)
1 (defines Harvard cache)
110 (defines 64 way)
110 (defines 64 way)
101 (defines 16KB)
101 (defines 16KB)
Value
0110
000
000
000
0
0
ARM920T PROCESSOR