s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 349

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s3c2410a

Manufacturer Part Number
s3c2410a
Description
16/32-bit Risc Arm Microprocessor
Manufacturer
Samsung Semiconductor, Inc.
Datasheet

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S3C2410A
14
OVERVIEW
The interrupt controller in the S3C2410A receives the request from 56 interrupt sources. These interrupt sources are
provided by internal peripherals such as the DMA controller, the UART, IIC, and others. In these interrupt sources,
the UARTn and EINTn interrupts are 'OR'ed to the interrupt controller.
When receiving multiple interrupt requests from internal peripherals and external interrupt request pins, the interrupt
controller requests FIQ or IRQ interrupt of the ARM920T core after the arbitration procedure.
The arbitration procedure depends on the hardware priority logic and the result is written to the interrupt pending
register, which helps users notify which interrupt is generated out of various interrupt sources.
(without sub -register)
(with sub -register)
Request sources
Request sources
INTERRUPT CONTROLLER
SUBSRCPND
Figure 14-1. Interrupt Process Diagram
SUBMASK
SRCPND
MODE
MASK
INTERRUPT CONTROLLER
Priority
INTPND
IRQ
FIQ
14-1

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