s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 313

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
UART CONTROL REGISTER
There are three UART control registers including UCON0, UCON1 and UCON2 in the UART block.
Clock Selection
Tx Interrupt Type
Rx Interrupt Type
Rx Time Out
Enable
Rx Error Status
Interrupt Enable
Loopback Mode
Reserved
Register
UCON0
UCON1
UCON2
UCONn
[10]
Bit
[9]
[8]
[7]
[6]
[5]
[4]
0x50000004
0x50004004
0x50008004
Address
Select PCLK or UEXTCLK for the UART baud rate.
0=PCLK : UBRDIVn = (int)(PCLK / (bps x 16) ) -1
1=UEXTCLK(@GPH8) : UBRDIVn = (int)(UEXTCLK / (bps x 16) ) -1
Interrupt request type.
0 = Pulse (Interrupt is requested as soon as the Tx buffer becomes
empty in Non-FIFO mode or reaches Tx FIFO Trigger Level in FIFO
mode.)
1 = Level (Interrupt is requested while Tx buffer is empty in Non-FIFO
mode or reaches Tx FIFO Trigger Level in FIFO mode.)
Interrupt request type.
0 = Pulse (Interrupt is requested the instant Rx buffer receives the
data in Non-FIFO mode or reaches Rx FIFO Trigger Level in FIFO
mode.)
1 = Level (Interrupt is requested while Rx buffer is receiving data in
Non-FIFO mode or reaches Rx FIFO Trigger Level in FIFO mode.)
Enable/Disable Rx time out interrupt when UART FIFO is enabled.
The interrupt is a receive interrupt.
0 = Disable
Enable the UART to generate an interrupt upon an exception, such as
a frame error, or overrun error during a receive operation.
0 = Do not generate receive error status interrupt.
1 = Generate receive error status interrupt.
Setting loopback bit to 1 causes the UART to enter the loopback
mode. This mode is provided for test purposes only.
0 = Normal operation
Reserved
R/W
R/W
R/W
R/W
UART channel 0 control register
UART channel 1 control register
UART channel 2 control register
1 = Loopback mode
1 = Enable
Description
Description
Reset Value
Initial State
0x00
0x00
0x00
0
0
0
0
0
0
0
11-11
UART