s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 253

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
DMA MASK TRIGGER (DMASKTRIG) REGISTER
NOTE:
STOP
ON_OFF
SW_TRIG
DMASKTRIGn
DMASKTRIG0
DMASKTRIG1
DMASKTRIG2
DMASKTRIG3
Register
You can freely change the values of DISRC register, DIDST registers, and TC field of DCON register.
Those changes take effect only after the finish of current transfer (i.e. when CURR_TC becomes 0). On the other
hand, any change made to other registers and/or fields takes immediate effect. Therefore, be careful in changing
those registers and fields.
0x4B0000A0
0x4B0000E0
0x4B000020
0x4B000060
Address
Bit
[2]
[1]
[0]
Stop the DMA operation.
1: DMA stops as soon as the current atomic transfer ends. If
NOTE: Due to possible current atomic transfer, “stop” operation
DMA channel on/off bit.
0: DMA channel is turned off. (DMA request to this channel is
1: DMA channel is turned on and the DMA request is handled.
NOTE: This bit should not be changed manually during DMA
Trigger the DMA channel in S/W request mode.
1: it requests a DMA operation to this controller.
Note that this trigger gets effective after S/W request mode has
to be selected (DCONn[23]) and channel ON_OFF bit has to be
set to 1 (channel on). When DMA operation starts, this bit is
cleared automatically.
This bit is automatically set to off if we set the DCONn[22] bit
to “no auto reload” and/or STOP bit of DMASKTRIGn to “stop”.
Note that when DCON[22] bit is "no auto reload", this bit
becomes 0 when CURR_TC reaches 0. If the STOP bit is 1,
this bit becomes 0 as soon as the current atomic transfer is
completed.
ignored.)
there is no current running atomic transfer, DMA stops
immediately. The CURR_TC will be 0.
operations (i.e. this has to be changed only by using
DCON[22] or STOP bit).
may take several cycles. The finish of the operation (i.e.
actual stop time) can be detected as soon as the channel
on/off bit (DMASKTRIGn[1]) is set to off. This stop is “actual
stop”.
R/W
R/W
R/W
R/W
R/W
DMA 0 mask trigger register
DMA 1 mask trigger register
DMA 2 mask trigger register
DMA 3 mask trigger register
Description
Description
Reset Value
Initial State
000
000
000
000
0
0
0
DMA
8-13