MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 100

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Electrical Characteristics
4.3.10
ETM is an ARM protocol. There are no inherent restrictions on operating frequency, other than ASIC pad
technology and TPA limitations. ASIC designers must provide a TRACECLK as symmetrical as possible,
and with set-up and hold times as large as possible. TPA designers must conversely be able to support a
TRACECLK as asymmetrical as possible, and require set up and hold times as short as possible. The
timing specifications in this section are given as a guide for a TPA that supports TRACECLK frequencies
up to around 100 MHz.
If a designer adheres to the timing described here, he or she can use any ARM-approved TPA.
depicts the TRACECLK timings of ETM, and
100
DQS (input)
DQ (input)
SD21
SD22
SD23
ID
SDCLK
SDCLK
Figure 41. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram
ETM Electrical Specifications
SDRAM CLK and DQS related parameters are being measured from the
50% point—that is, high is defined as 50% of signal value and low is defined
as 50% of signal value.
Actual processor clock frequencies vary according to application
requirements and the silicon process technologies used. The maximum
operating clock frequencies attained by ARM devices increases over time as
a result.
DQS - DQ Skew (defines the Data valid window in
read cycles related to DQS).
DQS DQ HOLD time from DQS
DQS output access time from SDCLK posedge
Table 39. Mobile DDR SDRAM Read Cycle Timing Parameters
SD23
i.MX31/i.MX31L Advance Information, Rev. 1.4
Parameter
SD21
Data
SD22
Data
Table 40
Preliminary
NOTE
NOTE
Data
lists the timing parameters.
Data
tDQSCK
Symbol
tDQSQ
tQH
Data
Data
Min
2.3
–
–
Freescale Semiconductor
Data
Max
.85
6.7
–
Data
Figure 42
Unit
ns
ns
ns