MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 10

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Functional Description and Application Information
2.3.5
The CSPI is used for fast data communication with fewer software interrupts. There are three identical
CSPI modules in the i.MX31 and i.MX31L that provide full-duplex synchronous serial interface. It is
master/slave configurable and includes four chip selects to support multiple peripherals. In addition, the
transfer continuation function of the CSPI allows unlimited length data transfers using 32-bit wide by 8
entry FIFO for both TX and RX data DMA support. The CSPI is equipped with data FIFOs and is a
master/slave configurable serial peripheral interface module, capable of interfacing to both SPI master and
slave devices. The CSPI Ready (SPI_RDY) and Chip Select (SS) control signals enable fast data
communication with fewer software interrupts. When the CSPI module is configured as a master, it uses a
serial link to transfer data between the CSPI and an external device. A chip-enable signal and a clock signal
are used to transfer data between these two devices. When the CSPI module is configured as a slave, the
user can configure the CSPI Control register to match the external SPI master’s timing.
2.3.6
The ECT scheme is based on the ECT debugging hardware from ARM Ltd. The ECT is composed of three
CTIs (Cross Trigger Interface) and one CTM (Cross Trigger Matrix). The ECT is key in the multi-core and
multi-IP debug strategy. The outcome is a SW-controlled debug signal matrix that receives many signals
from various sources (i.e. cores and peripherals) and propagates/routes them to the different debug
resources of the SoC. As seen in previous sections, those debug resources can include profiling
capabilities, real-time trace (trace enabled or disabled), triggers, SOC level multiplexing, and debug
interrupts.
The main advantages of using the ECT are that it provides a standardized debug scheme, in line with ARM
RealView debugger, simplifies integration with ARM debug tools. Another advantage is that within a
single debug domain, all the IPs can share the same debug resources and there is no need to duplicates
counters or real-time trace resources. One trace port can be used with one tool to track the activity of the
core and its peripherals. Since ECT should only be used during debug sessions, it is off (disabled) by
default.
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Dynamic Process Temperature Compensation (DPTC) reduces active power consumption by
adjusting supply voltage accordingly specific process cases, the manner in which the chip was
fabricated, and the ambient temperature.
State Retention Voltage (SRV) reduces static power consumption by decreasing supply voltage to
minimum State Retention level. Chip is not functional in this mode.
Active Well Bias (AWB) reduces static power consumption by applying back bias on transistors.
AWB can be applied on ARM11P. ARM11P is not functional when AWB is applied.
L2 Cache Power Gating—Reduces static power consumption by eliminating L2 Cache leakage.
ARM11P Power Gating—Reduces static power consumption by eliminating ARM11P leakage.
Configurable Serial Peripheral Interface (CSPI)
Embedded Cross Trigger (ECT)
i.MX31/i.MX31L Advance Information, Rev. 1.4
Preliminary
Freescale Semiconductor