MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 8

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Functional Description and Application Information
2.3
This section provides a brief text description of all the modules included in the i.MX31 and i.MX31L,
arranged in alphabetical order.
2.3.1
The 1-Wire module provides bi-directional communication between the ARM11 core and the
Add-Only-Memory EPROM (DS2502). The 1-Kbit EPROM is used to hold information about battery and
communicates with the ARM11 platform using the IP interface. The ARM11 (through the 1-Wire
interface) acts as the bus master and the DS2502 device is the slave. The 1-Wire peripheral does not trigger
interrupts; hence it is necessary for the ARM11 to poll of the 1-Wire to manage the module. The 1-Wire
uses an external pin(to connect to the DS2502. Timing requirements are met in hardware with the help of
a 1 MHz clock. The clock divider generates a 1 MHz clock that is used as time reference by the state
machine. Timing requirements are crucial for proper operation, and the 1-Wire state machine and the
internal clock provide the necessary signal. The clock must configured to approximately 1 MHz. You can
then set the 1-Wire register to send and receive bits over the 1-Wire bus.
2.3.2
The ATA block provides an AT attachment host interface for the i.MX31 and i.MX31L. Its main use is to
provide an interface with IDE hard disc drives and ATAPI optical disc drives. It interfaces with the ATA
device using industry standard ATA signals. The ATA interface is compliant to the ATA standard, and
supports following ATA standard protocols:
The ATA interface has two busses connected to it. The CPU bus provides communication with the ARM11
host processor and the DMA bus provides communication between the ATA module and the host DMA
unit. All internal ATA registers are visible from both busses, allowing enhanced DMA access to program
the interface.
There are basically two protocols that can be active at the same time on the ATA bus. The first and simplest
protocol (PIO mode access) can be started at any time by either the ARM11 or the host-enhanced DMA to
the ATA bus. The PIO mode is a slow protocol, mainly intended to be used to program an ATA disc drive,
but also possible to use to transfer data to/from the disc drive.
The second protocol is the DMA mode access. DMA mode is started by the ATA interface after receiving
a DMA request from the drive, and only if the ATA interface has been programmed to accept the DMA
request. In DMA mode, either multiword DMA or ultra DMA protocol is used on the ATA bus. All
transfers between FIFO and host IP or DMA IP bus are zero wait states transfer, so high speed transfer
between FIFO and DMA/host bus is possible.
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PIO modes 0, 1, 2, 3, and 4
Multiword DMA modes 0, 1, and 2
Ultra DMA modes 0, 1, 2, 3, and 4 with a bus clock of 50 MHz or higher
Ultra DMA mode 5 with bus clock of 80 MHz or higher
Module Descriptions
1-Wire
Advanced Technology Attachment (ATA)
i.MX31/i.MX31L Advance Information, Rev. 1.4
Preliminary
Freescale Semiconductor