MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 138

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Electrical Characteristics
4.3.20
Each SIM card interface consist of a total of 12 pins (for 2 separate ports of 6 pins each. Mostly one port
with 5 pins is used).
The interface is meant to be used with synchronous SIM cards. This means that the SIM module provides
a clock for the SIM card to use. The frequency of this clock is normally 372 times the data rate on the
TX/RX pins, however SIM module can work with CLK equal to 16 times the data rate on TX/RX pins.
There is no timing relationship between the clock and the data. The clock that the SIM module provides
to the aim card will be used by the SIM card to recover the clock from the data much like a standard UART.
All six (or 5 in case bi directional TXRX is used) of the pins for each half of the SIM module are
asynchronous to each other.
There are no required timing relationships between the pads in normal mode, but there are some in two
specific cases: reset and power down sequences.
4.3.20.1 General Timing Requirements
Figure 75
138
1
2
3
4
5
6
SDHC input / Card Outputs CMD, DAT (Reference to CLK)
In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
In normal data transfer mode for SD/SDIO card, clock frequency can be any value between 0 ~ 25 MHz.
In normal data transfer mode for MMC card, clock frequency can be any value between 0 ~ 20 MHz.
In card identification mode, card clock must be l100 kHz ~ 400 kHz, voltage ranges from 2.7 to 3.6 V.
In identification mode, card output delay time should be less than 50 ns.
In data transfer mode, card output delay time should be less than 14 ns.
SD8
ID
shows the timing of the SIM module, and
SIM Electrical Specifications
Card Output Delay Time during Data Transfer
Mode
Output Delay time during Identification Mode
CLK
Table 57. SDHC Interface Timing Parameters (continued)
Parameter
i.MX31/i.MX31L Advance Information, Rev. 1.4
Figure 75. SIM Clock Timing Diagram
Sfall
Preliminary
Figure 58
1/Sfreq
Symbol
t
t
ODLY
ODLY
Srise
5
6
lists the timing parameters.
Min
0
0
Max
14
50
Freescale Semiconductor
Unit
ns
ns