MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 21

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

SSI is typically used to transfer samples in a periodic manner. The SSI consists of independent transmitter
and receiver sections with independent clock generation and frame synchronization.
The SSI contains independent (asynchronous) or shared (synchronous) transmit and receive sections with
separate or shared internal/external clocks and frame syncs, operating in Master or Slave mode. The SSI
can work in normal mode operation using frame sync and in Network mode operation allowing multiple
devices to share the port with as many as thirty-two time slots. The SSI provides 2 sets of Transmit and
Receive FIFOs. Each of the four FIFOs is 8x24 bits. The two sets of Tx/Rx FIFOs can be used in Network
mode to provide 2 independent channels for transmission and reception. It also has programmable data
interface modes such like I2S, LSB, MSB aligned and programmable word lengths. Other program options
include frame sync and clock generation and programmable I2S modes (Master, Slave or Normal).
Oversampling clock, ccm_ssi_clk available as output from SRCK in I2S Master mode.
In addition to AC97 support the SSI has completely separate clock and frame sync selections for the
receive and transmit sections. In AC97 standard, the clock is taken from an external source and frame sync
is generated internally. the SSI also has a programmable internal clock divider and Time Slot Mask
Registers for reduced CPU overhead (for Tx and Rx both).
2.3.30
The i.MX31 and i.MX31L contain five UART modules, Each UART module is capable of standard
RS-232 non-return-to-zero (NRZ) encoding format and IrDA-compatible infrared modes. The UART
provides serial communication capability with external devices through an RS-232 cable or through use
of external circuitry that converts infrared signals to electrical signals (for reception) or transforms
electrical signals to signals that drive an infrared LED (for transmission) to provide low speed IrDA
compatibility.
The UART transmits and receives characters containing either 7 or 8 bits (program selectable). To
transmit, data is written from the IP data bus (Sky-Blue line interface) to a 32-byte transmitter FIFO
(TxFIFO). This data is passed to the shift register and shifted serially out on the transmitter pin (TXD). To
receive, data is received serially from the receiver pin (RXD) and stored in a 32-half-words-deep receiver
FIFO (RxFIFO). The received data is retrieved from the RxFIFO on the IP data bus. The RxFIFO and
TxFIFO generate maskable interrupts as well as DMA Requests when the data level in each of the FIFO
reaches a programmed threshold level.
The UART generates baud rates based on a dedicated input clock and its programmable divisor. The
UART also contains programmable auto baud detection circuitry to receive 1 or 2 stop bits as well as odd,
even, or no parity. The receiver detects framing errors, idle conditions, BREAK characters, parity errors,
and overrun errors.
2.3.31
The i.MX31 and i.MX31L provides three USB ports. The USB module provides high performance USB
On-The-Go (OTG) functionality, compliant with the USB 2.0 specification, the OTG supplement and the
ULPI 1.0 Low Pin Count specification. The module consists of 3 independent USB cores, each controlling
1 USB port.
Freescale Semiconductor
Universal Asynchronous Receiver/Transmitter (UART)
Universal Serial Bus (USB)
i.MX31/i.MX31L Advance Information, Rev. 1.4
Preliminary
Functional Description and Application Information
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