MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 22

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Functional Description and Application Information
In addition to the USB cores, the module provides for a Transceiverless Link (TLL) operation on host ports
1 and 2 and allows for routing the OTG transceiver interface to HOST port 1 such that this transceiver can
be used to communicate with a USB peripheral connected to host port 1.
The USB module has 2 connections to the CPU bus. One IP-bus connection for register accesses and one
AHB-bus connection for DMA transfer of data to and from the FIFOs.The USB module includes the
following features:
The USB module has 2 main modes of operation; Normal mode and Bypass mode. Furthermore, the USB
interfaces can be configured for High Speed operation (480 Mbps) and/or Full/Low speed operation
(12/1.5 Mbps). In normal mode, each USB core controls its corresponding PORT. Each port can work in
1 or more modes PHY mode: In this mode, an external serial transceiver is connected to the port. This is
used for off-board USB connections. TLL mode: In TLL mode, internal logic is enabled to emulate the
functionality of 2 back-to-back connected transceivers. This mode is typically used for on-board USB
connections to USB-capable peripherals. Host Port 2 supports ULPI and Serial Transceivers.
The OTG port requires a transceiver and is intended for off-board USB connections.
Serial Interface mode–In serial mode, a serial OTG transceiver must be connected. The port does not
support dedicated signals for OTG signaling. Instead, a transceiver with built-in OTG registers must be
used. Typically, the Transceiver registers are accessible over an I2C or SPI interface.
ULPI Mode–It this mode, a ULPI transceiver is connected to the port pins to support High-speed off board
USB connections. ULPI mode is activated by writing the following:
Bypass mode–Bypass mode affects the operation of the OTG port and HOST port 1. This mode is only
available when a serial transceiver is used on the OTG port, and the peripheral device on port 1 is using a
TLL connection.
Bypass mode is activated by setting the bypass bit in the USBCONTROL register. In this mode, the USB
OTG port connections are internally routed to the USB HOST 1 port, such that the transceiver on the OTG
port connects to a peripheral USB device on HOST port 1. The OTG core and the HOST 1 core are
disconnected from their ports when bypass is active.
Low Power mode–Each of the 3 USB cores has an associated power control module that is controlled by
the USB core and clocked on a 32 kHz clock. When a USB bus is idle, the tranceiver can be placed in low
power mode (suspend), after which the clocks to the USB core can be stopped. The 32 kHz low power
clock must remain active as it is needed for wakeup detection.
22
•
•
•
•
•
•
•
Full Speed / Low speed Host only core (HOST 1)
Transceiverless Link Logic (TLL) for on board connection to a FS/LS USB peripheral.
Bypass mode to route Host Port 1 signals to OTG I/O port
High Speed / Full Speed / Low Speed Host Only core (HOST2)
Full Speed / Low Speed interface for Serial transceiver.
TLL function for direct connection to USB peripheral in FS/LS (serial) operation
High speed OTG core
i.MX31/i.MX31L Advance Information, Rev. 1.4
Preliminary
Freescale Semiconductor