MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 105

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

A frame starts with a rising edge on SENSB_VSYNC (all the timings correspond to straight polarity of the
corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is valid
as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.
SENSB_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops
receiving data from the stream. For next line the SENSB_HSYNC timing repeats. For next frame the
SENSB_VSYNC timing repeats.
4.3.14.2.3
The timing is the same as the gated-clock mode (described in
page
clocks are valid and will cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is
inactive (states low) until valid data is going to be transmitted over the bus.
The timing described in
different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC;
active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.
Freescale Semiconductor
104), except for the SENSB_HSYNC signal, which is not used. See
SENSB_DATA[9:0]
SENSB_PIX_CLK
SENSB_DATA[7:0]
SENSB_HSYNC
SENSB_VSYNC
SENSB_PIX_CLK
SENSB_VSYNC
Non-Gated Clock Mode
Start of Frame
Start of Frame
Figure 46
invalid
invalid
Figure 46. Non-Gated Clock Mode Timing Diagram
nth frame
nth frame
Figure 45. Gated Clock Mode Timing Diagram
i.MX31/i.MX31L Advance Information, Rev. 1.4
1st byte
is that of a Motorola sensor. Some other sensors may have a slightly
1st byte
Active Line
Preliminary
n+1th frame
Section 4.3.14.2.2, “Gated Clock
invalid
n+1th frame
invalid
1st byte
1st byte
Figure
46. All incoming pixel
Electrical Characteristics
Mode”
on
105