MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 19

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Functional Description and Application Information
The SDMA memory is constituted of a ROM and a RAM. The ROM contains startup scripts (for example,
boot code) and other common utilities which are referenced by the scripts that reside in the RAM. The
internal RAM is divided into a context area and a script area.
Every transfer channel requires one context area to keep the contents of all the CORE and units registers
while it is inactive. Channel scripts are downloaded into the internal RAM by the SDMA using a dedicated
channel that is started during the boot sequence. Downloads are invoked using command and pointers
provided by the MCU or DSP. Every channel contains a corresponding channel script that is located in
RAM and/or ROM; and it can be reconfigured independently on an “as needed” basis. This permits a wide
range of SDMA functionality while using the lowest internal memory footprint possible. Channel scripts
can be stored in an external, large capacity, FLASH memory and downloaded when needed. The SDMA
can be configured with any mixture of scripts to enable an endless combination of supported services.
The scheduler is responsible for monitoring and detecting DMA requests, mapping them to channels and
mapping individual channels to a pre-configured priority. At any point in time, the scheduler will present
the highest priority channel requiring service to the SDMA core. A special SDMA core instruction is used
to “conditionally yield” the current channel being executed to an eligible channel that requires service. If,
and only if, an eligible channel is pending will the current execution of a channel be pre-empted. There are
two “yield” instructions that differently determine the eligible channels: in the first version, eligible
channels are pending channels with a strictly higher priority than the current channel priority; in the second
version (“yieldage”), eligible channels are pending channels with a priority that is greater or equal to the
current channel priority. The scheduler detects devices needing service through its 32 DMA request inputs.
After a request is detected, the scheduler determines the channel(s) that is (are) triggered by this request
and marks it (them) as pending in the “Channel Pending (EP)” register. The priorities of all the pending
channels are combined and continuously evaluated in order to update the highest pending priority. The
channel pending flag is cleared by the channel script when the transfer has completed.
The MCU Control module contains the control registers which are used to configure the 32 individual
channels. There are 32 Channel Enable Registers: every register is used to map one DMA request to any
desired combination of channels. The 32 Priority Registers are used to assign a programmable 1-of-7 level
priority to every possible channel. This module also contains all other control registers that can be accessed
by the MCU.
The DSP Control module, when available, contains a restricted set of registers that enable the DSP to
control the channels that have been allocated by the MCU approximately the same set of registers as the
MCU Control module. The SDMA is either owned by the MCU or the DSP, never by both at the same time
for security reasons. The master (MCU or DSP) that owns the SDMA is able to allocate channels to the
other master; the latter that is not controlling the SDMA has a limited access to its control registers.
The 32 DMA requests that are connected to the scheduler come from a variety of sources. The “receive
register full” and “transmit register empty” signals that are found in UART and USB ports are typical
examples of DMA requests that can be connected to the SDMA. These requests can be used to trigger a
specific SDMA channel, or several channels. This feature can be used to realize a “just-in-time” data
exchange between the two processors to relax the requirement to meet critical deadlines.
The embedded nature of the SDMA requires on-chip debug capability to assure product quality and
reliability and to realize the full performance capabilities of the core. The OnCE compatible debug port
i.MX31/i.MX31L Advance Information, Rev. 1.4
Freescale Semiconductor
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Preliminary