MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 14

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Functional Description and Application Information
The IIM consists of a master controller, a software fuse value shadow cache, and a set of registers to hold
the values of signals visible outside the module. Up to eight arrays of fuses (L-Fuses and/or e-Fuses) are
associated with the IIM, but are instantiated outside it.
The IIM is accessible via an 8-bit IP bus interface. An 8-bit interface is used because it matches the natural
width of the fuse arrays. All registers are 32-bit aligned, to allow the module to be instantiated on IP buses
supporting only 32-bit peripherals. A subset of fuses, as well as the software-controlled volatile signals,
are capable of driving top-level nets within the SoC. These signals are hereinafter referred to as
Hardware-Visible Signals, or HW-Visible Signals. These signals are intended for feature enablement and
disablement and similar uses within the device.
Laser fuses can only be blown during chip manufacturing (at the wafer level). The e-Fuses may be blown
under software or JTAG control during IC final test, at the customer factory or in the field. They include a
mechanism to inhibit further blowing of fuses (write-protect), to support secure computing environments.
The fuse values may also be overridden by software without modifying the fuse element. Similar to the
write-protect functionality, the override functionality can also be permanently disabled. Fuse banks may
also be scan-inhibited on a per-bank basis to prevent reading and programming of fuses through the JTAG
interface.
2.3.15
Image Processing Unit (IPU)
The IPU is designed to support video and graphics processing functions in the i.MX31 and i.MX31L and
to interface to video/still image sensors and displays. The IPU can capture image data from a camera
sensor or from a TV decoder. The captured image can be sent to preprocessing or stored in an external
system memory for additional processing on the ARM11 platform. Preprocessing of data can be
programmed from the sensor or from the external system memory. There are two preprocessing channels
determined by the data destination - an encoder or a display (viewfinder mode). Preprocessing includes
downsizing with independent integer horizontal and vertical ratios, resizing with independent fractional
horizontal and vertical ratios, color space conversion, combining a video plane with a graphics plane
(blending on graphics on top of video plane),
Data postprocessing from the external system memory. The MCU can invoke a number of postprocessing
channels sequentially by re-programming the IPU after finish of previous channel frame processing.
Postprocessing includes downsizing with independent integer horizontal and vertical ratios, resizing with
independent fractional horizontal and vertical ratios, color space conversion and combining a video plane
with a graphics plane (blending on graphics on top of video plane). It also provides 90 degree rotation,
up/down and left/right flipping of the image. Post-filtering of data from the system memory with support
of the MPEG-4 (both deblocking and deringing) and H.264 post-filtering algorithms.
The IPU provides for the display of video and graphics on a synchronous (dump or memoryless) display
by displaying video and graphics on an asynchronous (smart) display. There are two mechanisms to
support smart display or graphic accelerator functionality: interleaving data and commands from a
command buffer prepared by the MCU or automatic commands generation according to a prepared
template. The data can be sent to the smart display from the system memory, internal IPU processing
modules or directly from the MCU or the system DMA controller.
i.MX31/i.MX31L Advance Information, Rev. 1.4
14
Freescale Semiconductor
Preliminary