MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 78

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Electrical Characteristics
1
2. Make ton and toff big enough to avoid bus contention
4.3.5.4 UDMA Out Timing
Figure 16
host terminates transfer,
Table 28
78
There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last
active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.
Parameter
tdzfs
ATA
tzah
tcyc
tcvh
tmli
trp
–
–
lists the timing parameters for UDMA out burst.
shows timing when the UDMA out transfer starts,
Parameter
Figure
Figure
Figure 15
from
tmli1
tdzfs
tzah
tx1
tcvh
ton
toff
tc1
trp
1
13,
14,
Figure 18
Table 27. UDMA In Burst Timing Parameters (continued)
Figure 16. UDMA Out Transfer Starts Timing Diagram
(tcyc - tskew) > T
trp (min) = time_rp * T - (tskew1 + tskew2 + tskew6)
(time_rp * T) - (tco + tsu + 3T + 2 *tbuf + 2*tcable2) > trfs (drive)
tmli1 (min) = (time_mlix + 0.4) * T
tzah (min) = (time_zah + 0.4) * T
tdzfs = (time_dzfs * T) - (tskew1 + tskew2)
tcvh = (time_cvh *T) - (tskew1 + tskew2)
ton = time_on * T - tskew1
toff = time_off * T - tskew1
i.MX31/i.MX31L Advance Information, Rev. 1.4
shows timing when the UDMA out device terminates transfer, and
Preliminary
Description
Figure 17
shows timing when the UDMA out
Freescale Semiconductor
Controlling Variable
T big enough
time_mlix
time_dzfs
time_zah
time_cvh
time_rp
time_rp
–