MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 112

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Electrical Characteristics
4.3.15.4 Synchronous Interface to Dual-Port Smart Displays
Functionality and electrical characteristics of the synchronous interface to dual-port smart displays are
identical to parameters of the synchronous interface. See
TFT LCD Panels, Electrical
4.3.15.4.1
The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The bits
D7–D0 of the value are mapped to bits LD17–LD10 of the data bus, respectively.
interface timing,
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IP25
IP26
ID
Table 50. Sharp Synchronous Display Interface Timing Parameters—Pixel Level (continued)
The frequency of the clock DISPB_D3_CLK is 27 MHz (within 10%).
The DISPB_D3_HSYNC, DISPB_D3_VSYNC and DISPB_D3_DRDY signals are active low.
The transition to the next row is marked by the negative edge of the DISPB_D3_HSYNC signal. It
remains low for a single clock cycle.
The transition to the next field/frame is marked by the negative edge of the DISPB_D3_VSYNC
signal. It remains low for at least one clock cycle.
— At a transition to an odd field (of the next frame), the negative edges of DISPB_D3_VSYNC
— At a transition to an even field (of the same frame), they do not coincide.
The active intervals—during which data is transferred—are marked by the DISPB_D3_HSYNC
signal being high.
and DISPB_D3_HSYNC coincide.
PS rise time
REV toggle time
Interface to a TV Encoder,
Parameter
Characteristics”
i.MX31/i.MX31L Advance Information, Rev. 1.4
Symbol
Tpsr
on page
Trev
Functional Description
Preliminary
108.
PS_RISE_DELAY * Tdpcp
REV_TOGGLE_DELAY * Tdpcp
Section 4.3.15.2.2, “Interface to Active Matrix
Value
Figure 53
Freescale Semiconductor
depicts the
Units
ns
ns