MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 11

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

2.3.7
The EMI controls all memory accesses external to the i.MX31 and i.MX31L (read/write/erase/program)
from all the masters in the system. This is done by using two port interfaces MPG (AHB 32 bit) and
MPG64 (AHB 64 bit) toward different external memories.
The EMI includes interface elements, and controllers of external memories, as shown in the list below:
All accesses via the EMI are arbitrated by the Multi Master Memory Interface (M3IF) and controlled by
the respective memory controller. The M3IF - ESDCTL/MDDRC interface is designed to reduce access
latency by generating multiple accesses through the dedicated ESDCTL/MDDRC arbitration (MAB)
module, which controls the access towards/from the Enhanced SDRAM/MDDR memory controller. For
the other memory interfaces (PCMCIA, NFC, WEIM), the M3IF only arbitrates and forwards the masters
requests received through the Master Port Gasket (MPG/MPG64) interface.
The M3IF - Multi Master Memory Interface controls memory accesses (read/write/erase/program)
from one or more masters through different port interfaces toward different external memory controllers.
The masters arrive from the ARM Platform, the SDMA, the MPEG-4 encoder, or the IPU. The controllers
are: ESDCTL/MDDRC, PCMCIA, NANDFLASH and WEIM. The interface between the M3IF and the
controllers can be divided into two different types: M3IF-ESDCTL, and M3IF-all others. For the other port
interfaces, the M3IF arbitrates and forwards the masters’ requests received through the Master Port Gasket
(MPG) interfaces and the M3IF arbitration (M3A) module toward the respective memory controller.
The Enhanced SDRAM Controller consists of 10 major blocks, including the SDRAM command state
machine controller, bank register (page and bank address comparators), Row/Column Address Multiplexer
& decoder, configuration registers, refresh request sequencer, command sequencer, size logic (splitting
access), data path (data aligner/multiplexer), MDDR interface, and the Power Down timer. Since up to two
SDRAMs can be connected to the ESDCTL, and each SDRAM has 4 banks, there are a total of 8 bank
controllers. The bank controllers can also be used as comparators for timing parameters.
The NAND Flash Controller (NFC) interfaces standard NAND Flash devices to the i.MX31 and
i.MX31L and hides the complexities of accessing the NAND Flash. It provides a glueless interface to both
8-bits and 16-bits NAND Flash parts with page sizes of 512 Bytes or 2 Kilobytes. It addressing scheme
allows it to accesses flash devices of almost limitless capacities. The 2 kilobyte RAM buffer of the NAND
Flash is used as the boot RAM during a cold reset (if the i.MX31 and i.MX31L are configured for a boot
to be carried out from the NAND Flash device). After the boot procedure completes, the RAM is available
as buffer RAM. In addition, the NAND Flash controller provides an X16 bit and X32 bit interface to the
AHB bus on the chip side, and an X8/X16 interface to the NAND Flash device on the external side.
The Wireless External Interface Module (WEIM) handles the interface to devices external to chip,
including generation of chip selects, clocks and controls for external peripherals and memory. It provides
asynchronous and synchronous access to devices with SRAM-like interface.The WEIM includes six chip
Freescale Semiconductor
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M3IF—Multi Master Memory Interface.
ESDCTL/MDDRC—Enhanced SDRAM/MDDR memory controller.
PCMCIA—PCMCIA memory controller.
NFC—NAND Flash memory controller.
WEIM—SRAM/PSRAM/FLASH memory controller.
External Memory Interface (EMI)
i.MX31/i.MX31L Advance Information, Rev. 1.4
Preliminary
Functional Description and Application Information
11