MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 7

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Freescale Semiconductor
Mnemonic
SCC
SDHC
SDMA
SIM
SJC
SSI
UART
USB
WDOG
Block
Security
Controller
Module
Secured Digital
Host Controller
SDMA
Subscriber
Identification
Module
Secure JTAG
Controller
Synchronous
Serial Interface
Universal
Asynchronous
Receiver/Trans
mitter
Universal Serial
Bus—
2 Host
Controllers and
1 OTG
(On-The-Go)
Watchdog Timer
Module
Block Name
Security
Connectivity
Peripheral
System
Control
Peripheral
Connectivity
Peripheral
Debug
Multimedia
Peripheral
Connectivity
Peripheral
Connectivity
Peripherals
Timer
Peripheral
Functional
Grouping
Table 3. Digital and Analog Modules (continued)
i.MX31/i.MX31L Advance Information, Rev. 1.4
The SCC is a hardware component composed of two blocks—the
Secure RAM module, and the Security Monitor. The Secure RAM
provides a way of securely storing sensitive information. The
Security Monitor implements the security policy, checking algorithm
sequencing, and controlling the Secure State.
The SDHC controls the MMC (MultiMediaCard), SD (Secure
Digital) memory, and I/O cards by sending commands to cards and
performing data accesses to and from the cards.
The SDMA controller maximizes the system’s performance by
relieving the ARM core of the task of bulk data transfer from memory
to memory or between memory and on-chip peripherals.
The SIM interfaces to an external Subscriber Identification Card. It
is an asynchronous serial interface adapted for Smart Card
communication for e-commerce applications.
The SJC provides debug and test control with maximum security
and provides a flexible architecture for future derivatives or future
multi-cores architecture.
The SSI is a full-duplex, serial port that allows the chip to
communicate with a variety of serial devices, such as standard
codecs, Digital Signal Processors (DSPs), microprocessors,
peripherals, and popular industry audio codecs that implement the
inter-IC sound bus standard (I2S) and Intel AC97 standard.
The UART provides serial communication capability with external
devices through an RS-232 cable or through use of external
circuitry that converts infrared signals to electrical signals (for
reception) or transforms electrical signals to signals that drive an
infrared LED (for transmission) to provide low speed IrDA
compatibility.
The WDOG module protects against system failures by providing a
method for the system to recover from unexpected events or
programming errors.
• USB Host 1 is designed to support transceiverless connection to
• USB Host 2 is designed to support transceiverless connection to
• The USB-OTG controller offers HS/FS/LS capabilities in Host
the on-board peripherals in Low Speed and Full Speed mode,
and connection to the ULPI (UTMI+ Low-Pin Count) and Legacy
Full Speed transceivers.
the Cellular Modem Baseband Processor.
mode and HS/FS in device mode. In Host mode, the controller
supports direct connection of a FS/LS device (without external
hub). In device (bypass) mode, the OTG port functions as
gateway between the Host 1 Port and the OTG transceiver.
Preliminary
Functional Description and Application Information
Brief Description3
2.3.24/17
2.3.25/18
2.3.26/18
2.3.27/20
2.3.28/20
2.3.29/20
2.3.30/21
2.3.31/21
2.3.32/23
Section/
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