MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 151

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

4.3.23
This section describes the electrical information of the USBOTG port. The OTG port supports both serial
and parallel interfaces.
The high speed (HS) interface is supported via the ULPI (Ultra Low Pin Count Interface).
depicts the USB ULPI timing diagram, and
Freescale Semiconductor
USB Electrical Specifications
All the timings for the SSI are given for a non-inverted serial clock polarity
(TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the
polarity of the clock and/or the frame sync have been inverted, all the timing
remains valid by inverting the clock signal STCK/SRCK and/or the frame
sync STFS/SRFS shown in the tables and in the figures.
All timings are on AUDMUX pads when the SSI is being used for data
transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
For internal Frame Sync operation using external clock, the FS timing will
be same as that of Tx Data, for example, during the AC97 mode of
operation.
Table 64. SSI Receiver with External Clock Timing Parameters (continued)
SS25
SS26
SS28
SS30
SS32
SS34
SS35
SS36
SS40
SS41
ID
(Tx/Rx) CK clock low period
(Tx/Rx) CK clock fall time
(Rx) CK high to FS (bl) high
(Rx) CK high to FS (bl) low
(Rx) CK high to FS (wl) high
(Rx) CK high to FS (wl) low
(Tx/Rx) External FS rise time
(Tx/Rx) External FS fall time
SRXD setup time before (Rx) CK low
SRXD hold time after (Rx) CK low
i.MX31/i.MX31L Advance Information, Rev. 1.4
Parameter
Table 65
Preliminary
NOTE
NOTE
NOTE
NOTE
lists the timing parameters.
–10.0
–10.0
36.0
10.0
10.0
10.0
Min
2.0
–
–
–
Max
15.0
15.0
6.0
6.0
6.0
–
–
–
–
–
Electrical Characteristics
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 87
151