MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 130

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MCIMX31L

Manufacturer Part Number
MCIMX31L
Description
Multimedia Applications Processors
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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1
conditions may be chip specific.
2
3
4
5
6
7
8
9
10
chip-level output delay, board delays, a chip-level input delay, an IPU input delay. This value is chip specific.
Tdrp
Electrical Characteristics
IP56 Controls setup time for write
IP57 Controls hold time for write
IP58 Slave device data delay
IP59 Slave device data hold time
IP60 Write data setup time
IP61 Write data hold time
IP62 Read period
IP63 Write period
IP64 Read down time
IP65 Read up time
IP66 Write down time
IP67 Write up time
IP68 Read time point
The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These
Display interface clock period value for read:
Display interface clock period value for write:
Display interface clock down time for read:
Display interface clock up time for read:
Display interface clock down time for write:
Display interface clock up time for write:
Tdicuw
This parameter is a requirement to the display connected to the IPU.
Data read point:
130
Tdicdw
Tdicpw
Tdicdr
Tdicur
Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a
ID
Tdicpr
=
T
=
=
=
=
=
=
HSP_CLK
1
-- - T
2
1
-- - T
2
1
-- - T
2
1
-- - T
2
T
T
HSP_CLK
HSP_CLK
HSP_CLK
HSP_CLK
HSP_CLK
HSP_CLK
Table 52. Asynchronous Serial Interface Timing Parameters—Access Level (continued)
Parameter
ceil
2
3
ceil
ceil
7
5
ceil
ceil
ceil
ceil
------------------------------------------------- -
HSP_CLK_PERIOD
DISP#_READ_EN
9
6
4
DISP#_IF_CLK_PER_RD
--------------------------------------------------------------- -
DISP#_IF_CLK_PER_WR
----------------------------------------------------------------- -
2 DISP#_IF_CLK_DOWN_RD
-------------------------------------------------------------------------------
2 DISP#_IF_CLK_UP_WR
--------------------------------------------------------------------- -
2 DISP#_IF_CLK_UP_RD
--------------------------------------------------------------------
2 DISP#_IF_CLK_DOWN_WR
-------------------------------------------------------------------------------- -
HSP_CLK_PERIOD
HSP_CLK_PERIOD
HSP_CLK_PERIOD
HSP_CLK_PERIOD
HSP_CLK_PERIOD
HSP_CLK_PERIOD
8
8
Symbol
Tdicpw
Tdicdw
Tdicuw
Tdchw
Tdcsw
Tdicpr
Tdicdr
Tdicur
Tracc
i.MX31/i.MX31L Advance Information, Rev. 1.4
Tdrp
Troh
Tds
Tdh
Tdicuw-1.5
Tdicpw-Tdicdw-1.5
0
Tdrp-Tlbd-Tdicdr+1.5
Tdicdw-1.5
Tdicpw-Tdicdw-1.5
Tdicpr-1.5
Tdicpw-1.5
Tdicdr-1.5
Tdicur-1.5
Tdicdw-1.5
Tdicuw-1.5
Tdrp-1.5
Min.
Preliminary
Tdicuw
Tdicpw-Tdicdw
Tdicdw
Tdicpw-Tdicdw
Tdicpr
Tdicpw
Tdicdr
Tdicur
Tdicdw
Tdicuw
Tdrp
Typ.
1
Tdrp
Tdicpr-Tdicdr-1.5
Tdicpr+1.5
Tdicpw+1.5
Tdicdr+1.5
Tdicur+1.5
Tdicdw+1.5
Tdicuw+1.5
Tdrp+1.5
9
-Tlbd
Freescale Semiconductor
Max.
10
-Tdicur-1.5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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