MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 13

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

be programmed to be active in low power and debug modes Interrupt generation can be programmed for
capture, compare, rollover events and the timers offers both restart or free-run modes of operation.
2.3.12
The GPU provides hardware acceleration for 2D and 3D graphics algorithms. The quality is sufficient for
running desk-top quality interactive graphics applications on displays whose resolution is equivalent to
VGA (and above) and whose color representation is up to 32 bits per pixel. The i.MX31 and i.MX31L’s
GPU is built around an ARM MBX R-S graphics accelerator.
The GPU operates on 3D scene data (sent as batches of triangles) that are transformed and lit by the VGP.
Triangles are written directly to the TA on a First In First Out (FIFO) basis so that the CPU is not stalled.
In addition, the SDMA can be used to perform batch transfers with very low CPU involvement. The TA
performs advanced culling on triangle data by writing the tiled non-culled triangles to the external memory.
The event manager uses SmartBuffer technology for control. As a result, any level of scene complexity is
handled in a fixed display list buffer size. The HSR engine reads the tiled data and implements per-pixel
HSR with full Z-accuracy. The resulting visible pixels are textured and shaded in Internal True Color (ITC,
24 bit per pixel) before rendering the final image for display buffer.
2.3.13
I
minimizing the interconnection between devices. This bus is suitable for applications requiring occasional
communications over a short distance between many devices. The flexible I
to be connected to the bus for expansion and system development.
The I
please refer to Philips I
including arbitration and collision detection that prevents data corruption if multiple devices attempt to
control the bus simultaneously. This feature supports complex applications with multiprocessor control
and can be used for rapid testing and alignment of end products through external connections to an
assembly-line computer.
2.3.14
The IIM provides an interface for reading and in some cases programming and/or overriding identification
and control information stored in on-chip fuse elements. The module supports laser fuses (L-Fuses) or
electrically-programmable poly fuses (e-Fuses) or both kinds.
The IIM also provides a set of volatile software-accessible signals which can be used for software control
of hardware elements, not requiring non-volatility. The IIM provides the primary user-visible mechanism
for interfacing with on-chip fuse elements. Among the uses for the fuses are unique chip identifiers, mask
revision numbers, cryptographic keys, and various control signals requiring permanent non-volatility. The
IIM also provides up to 28 volatile control signals and a means to generate a second 168-bit SCC key.
Freescale Semiconductor
2
C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange,
2
C operates up to 400 kbps but it depends on the pad loading and timing (for pad requirement details
Graphics Processing Unit (GPU)
Inter IC Communication (I
IC Identification Module (IIM)
2
C Bus Specification, Version 2.1). The I
The GPU is not available on the i.MX31L.
i.MX31/i.MX31L Advance Information, Rev. 1.4
2
C)
Preliminary
NOTE
Functional Description and Application Information
2
C system is a true multiple-master bus
2
C allows additional devices
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