MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 111

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MCIMX31L

Manufacturer Part Number
MCIMX31L
Description
Multimedia Applications Processors
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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4.3.15.3 Interface to Sharp HR-TFT Panels
Figure 52
CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY,
REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and
SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to
Section 4.3.15.2.2, “Interface to Active Matrix TFT LCD Panels, Electrical Characteristics” on page 108.
The timing images correspond to straight polarity of the Sharp signals.
Freescale Semiconductor
DISPB_D3_DATA
IP21
IP22
IP23
IP24
DISPB_D3_SPL
DISPB_D3_CLS
DISPB_D3_REV
ID
DISPB_D3_PS
DISPB_D3_CLK
DISPB_D3_HSYNC
depicts the Sharp HR-TFT panel interface timing, and
SPL rise time
CLS rise time
CLS fall time
CLS rise and PS fall time
Table 50. Sharp Synchronous Display Interface Timing Parameters—Pixel Level
Figure 52. Sharp HR-TFT Panel Interface Timing Diagram—Pixel Level
Parameter
SPL pulse width is fixed and aligned to the first data of the line.
Example is drawn with FW+1=320 pixel/line, FH+1=240 lines.
REV toggles every HSYNC period.
IP24
IP22
i.MX31/i.MX31L Advance Information, Rev. 1.4
Horizontal timing
IP21
IP23
Symbol
Tsplr
Tclsr
Tclsf
Tpsf
IP25
Preliminary
D1 D2
IP26
1 DISPB_D3_CLK period
(BGXP - 1) * Tdpcp
CLS_RISE_DELAY * Tdpcp
CLS_FALL_DELAY * Tdpcp
PS_FALL_DELAY * Tdpcp
Table 50
D320
Value
lists the timing parameters. The
Electrical Characteristics
Units
ns
ns
ns
ns
111

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