MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 90

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Electrical Characteristics
90
1
2
3
WE10
WE11
WE12
WE13
WE14
WE15
WE16
WE15
WE16
WE17
WE18
WE17
WE18
WE19
WE20
WE20
WE21
WE22
WE23
Not required.
BCLK parameters are being measured from the 50% VDD.
The actual cycle time is derived from the AHB bus clock frequency.
WE4
WE5
WE6
WE7
WE8
WE9
ID
High is defined as 80% of signal value and low is defined as 20% of signal value.
Input Data Valid to Clock rise, FCE=0
Input Data Valid to Clock rise, FCE=1
Clock rise/fall to CS[x] invalid
Clock rise/fall to RW Valid
Clock rise/fall to RW Invalid
Clock rise/fall to OE Valid
Clock rise/fall to OE Invalid
Clock rise/fall to EB[x] Valid
Clock rise/fall to EB[x] Invalid
Clock rise/fall to LBA Valid
Clock rise/fall to LBA Invalid
Clock rise/fall to Output Data Valid
Clock rise to Output Data Invalid
Cloc/k rise to Input Data Invalid, FCE=0
Clock rise to Input Data Invalid, FCE=1
ECB setup time, FCE=0
ECB hold time, FCE=0
ECB setup time, FCE=1
ECB hold time, FCE=1
DTACK setup time
DTACK hold time
DTACK hold time (Level sensitive mode, EW=1
implies wsc < 111111)
BCLK High Level Width
BCLK Low Level Width
BCLK Cycle time
Table 33. WEIM Bus Timing Parameters (continued)
2
1
i.MX31/i.MX31L Advance Information, Rev. 1.4
2, 3
2, 3
Parameter
Preliminary
NOTE
–3.5
–3.5
Min
–3
–3
–7
–2
–2
–3
–3
–3
–3
–3
–3
–3
–2
–2
–7
–7
–7
–
0
6
–
–
–
1.8 V
Tcycle/
Tcycle/
Max
2-3
2-3
Freescale Semiconductor
10
10
10
10
12
10
10
3
3
3
3
3
3
3
3
3
0
0
–
0
0
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns