MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 124

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

1
These conditions may be chip specific.
2
3
4
5
6
7
8
9
10
chip-level output delay, board delays, a chip-level input delay, an IPU input delay. This value is chip specific.
Electrical Characteristics
124
IP36 Controls hold time for write
IP37 Slave device data delay
IP38 Slave device data hold time
IP39 Write data setup time
IP40 Write data hold time
IP41 Read period
IP42 Write period
IP43 Read down time
IP44 Read up time
IP45 Write down time
IP46 Write up time
IP47 Read time point
Tdicdr
Tdicuw
Tdicpw
The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
Display interface clock period value for read:
Display interface clock period value for write:
Display interface clock down time for read:
Display interface clock up time for read:
Tdicur
Display interface clock down time for write:
Display interface clock up time for write:
This parameter is a requirement to the display connected to the IPU
Data read point
Tdrp
Tdicpr
Tdicdw
Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a
ID
=
=
=
=
T
=
=
=
HSP_CLK
1
-- - T
2
1
-- - T
2
T
1
-- - T
2
T
1
-- - T
2
HSP_CLK
Table 51. Asynchronous Parallel Interface Timing Parameters—Access Level (continued)
HSP_CLK
HSP_CLK
HSP_CLK
HSP_CLK
HSP_CLK ceil
Parameter
⋅
ceil
⋅
⋅
⋅
2
3
ceil
⋅
ceil
⋅
ceil
ceil
7
⋅
5
ceil
------------------------------------------------- -
HSP_CLK_PERIOD
DISP#_READ_EN
9
6
DISP#_IF_CLK_PER_RD
--------------------------------------------------------------- -
4
DISP#_IF_CLK_PER_WR
----------------------------------------------------------------- -
2 DISP#_IF_CLK_DOWN_RD
-------------------------------------------------------------------------------
2 DISP#_IF_CLK_UP_RD
--------------------------------------------------------------------
2 DISP#_IF_CLK_UP_WR
--------------------------------------------------------------------- -
2 DISP#_IF_CLK_DOWN_WR
-------------------------------------------------------------------------------- -
HSP_CLK_PERIOD
⋅
⋅
HSP_CLK_PERIOD
⋅
⋅
HSP_CLK_PERIOD
HSP_CLK_PERIOD
HSP_CLK_PERIOD
HSP_CLK_PERIOD
8
8
Symbol
Tdicpw Tdicpw-1.5
Tdicdw Tdicdw-1.5
Tdicuw Tdicuw-1.5
Tdchw Tdicpw-Tdicdw-1.5
Tdicpr
Tdicdr
Tdicur
Tracc
i.MX31/i.MX31L Advance Information, Rev. 1.4
Tdrp
Troh
Tdh
Tds
0
Tdrp-Tlbd-Tdicdr+1.5
Tdicdw-1.5
Tdicpw-Tdicdw-1.5
Tdicpr-1.5
Tdicdr-1.5
Tdicur-1.5
Tdrp-1.5
Min.
Preliminary
Tdicpw-Tdicdw
Tdicdw
Tdicpw-Tdicdw
Tdicpr
Tdicpw
Tdicdr
Tdicur
Tdicdw
Tdicuw
Tdrp
Typ.
–
–
1
Tdicpr+1.5
Tdicdr+1.5
Tdicur+1.5
Tdrp
Tdicpr-Tdicdr-1.5
Tdicpw+1.5
Tdicdw+1.5
Tdicuw+1.5
Tdrp+1.5
9
-Tlbd
Freescale Semiconductor
Max.
10
–
–
–
-Tdicur-1.5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns