MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 109

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Table 48
Freescale Semiconductor
1
Display interface clock period average value.
DISPB_D3_HSYNC
Display interface clock period immediate value.
DISPB_D3_VSYNC
DISPB_D3_DRDY
IP10
IP12
IP13
IP14
IP15
IP5
IP6
IP7
IP8
IP9
Tdicp
ID
shows timing parameters of signals presented in
=
⎧
⎪
⎪
⎨
⎪
⎪
⎩
IP11
Display interface clock period
Display pixel clock period
Screen width
HSYNC width
Horizontal blank interval 1
Horizontal blank interval 2
Screen height
VSYNC width
Vertical blank interval 1
Vertical blank interval 2
T HSP_CLK
Table 48. Synchronous Display Interface Timing Parameters—Pixel Level
T HSP_CLK
Figure 50. TFT Panels Timing Diagram—Vertical Sync Pulse
Parameter
⋅
⎛
⎝
floor
⋅
DISP3_IF_CLK_PER_WR
----------------------------------------------------------------- -
HSP_CLK_PERIOD
IP13
Tdicp
DISP3_IF_CLK_PER_WR
----------------------------------------------------------------- -
i.MX31/i.MX31L Advance Information, Rev. 1.4
HSP_CLK_PERIOD
=
T HSP_CLK
IP14
Symbol
Tdpcp
Preliminary
Tdicp
Thbi1
Thbi2
Tvbi1
Tvbi2
Thsw
Tvsw
,
Tsw
⋅
Tsh
DISP3_IF_CLK_PER_WR
----------------------------------------------------------------- -
HSP_CLK_PERIOD
+
0.5 0.5
Figure 49
±
(
(DISP3_IF_CLK_CNT_D+1) * Tdicp
(SCREEN_WIDTH+1) * Tdpcp
(H_SYNC_WIDTH+1) * Tdpcp
BGXP * Tdpcp
(SCREEN_WIDTH - BGXP - FW) * Tdpcp
(SCREEN_HEIGHT+1) * Tsw
if V_SYNC_WIDTH_L = 0 than
(V_SYNC_WIDTH+1) * Tdpcp
else
(V_SYNC_WIDTH+1) * Tsw
BGYP * Tsw
(SCREEN_HEIGHT - BGYP - FH) * Tsw
1
)
⎞
⎠
Start of frame
,
IP12
for integer
for fractional
and
Figure
Value
DISP3_IF_CLK_PER_WR
----------------------------------------------------------------- -
HSP_CLK_PERIOD
DISP3_IF_CLK_PER_WR
----------------------------------------------------------------- -
50.
HSP_CLK_PERIOD
End of frame
Electrical Characteristics
IP15
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
109