MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 9

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

2.3.3
The AUDMUX provides programmable interconnecting for voice, audio, and synchronous data routing
between host serial interfaces (i.e. SSI, SAP) and peripheral serial interfaces (i.e. audio and voice codecs).
The AUDMUX allows audio system connectivity to be modified through programming (as opposed to
altering the design of the system into which the chip is designed). The design of the AUDMUX allows
multiple simultaneous audio/voice/data flows between the ports in point-to-point or point-to-multipoint
configurations.
Included in the AUDMUX are two types of interfaces. The internal ports connect to the processor serial
interfaces and external ports connect to off-chip audio devices and serial interfaces of other processors. A
desired connectivity is achieved by configuring the appropriate internal and external ports.
The module includes full 6-wire SSI interfaces for asynchronous receive and transmit as well as a
configurable 4-wire (synchronous) or 6-wire (asynchronous) peripheral interface The AUDMUX allows
each host interface to be connected to any other host or peripheral interface in a point-to-point or
point-to-multipoint (network mode).
2.3.4
The CCM controls the system frequency, distributes clocks to various parts of the chip, controls the reset
mechanism of the chip, and provides an advanced low-power management capability of the i.MX31 and
i.MX31L.
The CCM utilizes multiple clock sources to generate the clock signals in the i.MX31 and i.MX31L. The
external low frequency clock (CKIL) can use either a 32 kHz, 32.768 kHz or a 38.4 kHz crystal as its
source. For applications that require a high frequency clock source the CCM has a CKIH pin to which an
external high frequency clock can be connected.
The CCM provides a large number of clock outputs used to supply clocks to the MCU and the peripherals.
The i.MX31 and i.MX31L are partitioned into two asynchronous clock domains: MCU and USB, as there
are different functionality and frequency requirements from these clocks. The main clock of the MCU
clock domain is mcu_main_clk and is generated by MCU clock switch unit. The MCU clock domain is
partitioned into four synchronous clocks and two sub-domains. The main clock of this domain is called
mcu_main_clk, and it is the output of the MCU clock switch unit. The main clock of the USB clock domain
is usb_main_clk and is generated by the USB clock switch unit.
Another part of the CCM is the low-power clock gating (LPCG). The LPCG block distributes clocks to all
modules from the subdomain clocks and gates off clocks in low-power mode. Clock gating for each
module is carried out based on the specific low-power mode and the relevant bits in the MCGR register.
The power management portion of the i.MX31 and i.MX31L is controlled by the CCM. To this end, the
i.MX31 and i.MX31L are partitioned into four power domains. The i.MX31 and i.MX31L support a
versatile definition of power modes, including power and clock domains status and applied power
techniques. The power modes are Run, Wait, Doze, State Retention, Deep Sleep, and Hibernate. The CCM
supports several power management techniques that reduce active and static power consumption:
Freescale Semiconductor
•
Dynamic Voltage Frequency Scaling (DVFS) reduces active power consumption by scaling voltage
and frequency accordingly to required MIPs.
Digital Audio Mux (AUDMUX)
Clock Control Module (CCM)
i.MX31/i.MX31L Advance Information, Rev. 1.4
Preliminary
Functional Description and Application Information
9