MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 12

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Functional Description and Application Information
selects for external devices, with two CS signals covering a range of 128Mbytes, and the other four each
covering a range of 32Mbytes.The 128 Mbyte range can be increased to 256Mbytes when combined with
combining the two signals. The WEIM offers selectable protection for each chip select as well as
programmable data port size. There is a programmable wait-state generator for each chip select and
support for Big Endian and Little Endian modes of operation per access.
2.3.8
The EPIT is a 32-bit “set and forget” timer which starts counting after the EPIT is enabled by software and
can generate an interrupt generation when counter reaches the Compare value. It is capable of providing
precise interrupts at regular intervals with minimal processor intervention.The EPIT is based on a 32-bit
down counter with selectable clock. It also has a 12-bit prescaler for division of input clock frequency. The
counter value can be programmed on the fly and can also be programmed to be active in both low power
and debug modes.
2.3.9
The Fast InfraRed Interface module (FIR) is capable of establishing a 0.576 Mbit/s, 1.152 Mbit/s or 4
Mbit/s half duplex link via a LED and IR detector. It supports 0.576 Mbit/s, 1.152 Mbit/s Medium InfraRed
(MIR) physical layer protocol and 4Mbit/s Fast InfraRed (FIR) physical layer protocol defined by IrDA,
version 1.4. In addition, the Serial InfraRed (SIR) protocol, which supports data rate 115.2kbps or lower,
is implemented in UART module. The FIR interface signals are multiplexed with the UART counterpart
signals via GPIO configuration for a complete InfraRed Interface supporting SIR, MIR and FIR modes.
2.3.10
The general-purpose input/output (GPIO) peripheral provides dedicated general-purpose pins that can be
configured as either inputs or outputs. When configured as an output, you can write to an internal register
to control the state driven on the output pin. When configured as an input, you can detect the state of the
input by reading the state of an internal register. The GPIO includes all of the general purpose input/output
logic necessary to drive a specific data to the pad and control the direction of the pad using registers in the
GPIO module. The ARM11 is able to sample the status of the corresponding pads by reading the
appropriate status register. The GPIO supports up to 32 interrupts and has the ability to identify interrupt
edges as well as generate three active high interrupts.
2.3.11
The General purpose timer (GPT) has a 32 bit up-counter. The timer counter value can be captured in a
register using an event on an external pin. The capture trigger can be programmed to be a rising or/and
falling edge. The GPT can also generate an event on ipp_do_cmpout pins and an interrupt when the timer
reaches a programmed value. It has a 12-bit prescaler providing a programmable clock frequency derived
from multiple clock sources. The GPT has one 32 bit up-counter with clock source selection, including
external clock, two input capture channels with programmable trigger edge, and three output compare
channels with programmable output mode. The GPT can perform a forced compare and can configured to
12
Enhanced Periodic Interrupt Timer (EPIT)
Fast InfraRed Interface (FIR)
General Purpose I/O Module (GPIO)
General Purpose Timer (GPT)
i.MX31/i.MX31L Advance Information, Rev. 1.4
Preliminary
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