MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 110

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

1
These conditions may be chip specific.
2
3
where CEIL(X) rounds the elements of X to the nearest integers towards infinity.
Electrical Characteristics
The SCREEN_WIDTH, SCREEN_HEIGHT, H_SYNC_WIDTH, V_SYNC_WIDTH, BGXP, BGYP and
V_SYNC_WIDTH_L parameters are programmed via the SDC_HOR_CONF, SDC_VER_CONF,
SDC_BG_POS Registers. The FW and FH parameters are programmed for the corresponding DMA
channel. The DISP3_IF_CLK_PER_WR, HSP_CLK_PERIOD and DISP3_IF_CLK_CNT_D parameters
are programmed via the DI_DISP3_TIME_CONF, DI_HSP_CLK_PER and DI_DISP_ACC_CC
Registers.
Figure 51
parameters. The DISP3_IF_CLK_DOWN_WR and DISP3_IF_CLK_UP_WR parameters are set via the
DI_DISP3_TIME_CONF Register.
110
The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
IP16
IP17
IP18
IP19
IP20
Display interface clock down time
Display interface clock up time
ID
DISPB_D3_VSYNC
DISPB_D3_HSYNC
DISPB_D3_DRDY
DISPB_D3_CLK
Display interface clock
low time
Display interface clock
high time
Data setup time
Data holdup time
Control signals setup
time to display interface
clock
other controls
depicts the synchronous display interface timing for access level, and
DISPB_DATA
Parameter
Table 49. Synchronous Display Interface Timing Parameters—Access Level
Figure 51. Synchronous Display Interface Timing Diagram—Access Level
IP16
Tdicd
Tdicu
Symbol
Tdsu
Tdhd
Tckh
Tcsu
Tckl
i.MX31/i.MX31L Advance Information, Rev. 1.4
=
IP17
=
1
-- - T
2
1
-- - T
2
HSP_CLK ceil
Tdicd-Tdicu-1.5
Tdicp-Tdicd+Tdicu-1.5
Tdicd-3.5
Tdicp-Tdicd-3.5
Tdicd-3.5
HSP_CLK ceil
⋅
Min
IP19
⋅
Preliminary
2 DISP3_IF_CLK_DOWN_WR
-------------------------------------------------------------------------------- -
⋅
2 DISP3_IF_CLK_UP_WR
--------------------------------------------------------------------- -
⋅
IP18
HSP_CLK_PERIOD
HSP_CLK_PERIOD
IP20
Tdicp-Tdicd+Tdicu
Tdicu
Tdicp-Tdicu
Tdicu
Tdicd
2
-Tdicu
Typ
1
3
Tdicp-Tdicd+Tdicu+1.5
Tdicd-Tdicu+1.5
Table 49
Freescale Semiconductor
Max
–
lists the timing
Units
ns
ns
ns
ns
ns