MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 18

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Functional Description and Application Information
(specifically platform test access signals). It also serves as a device unique data protection/encryption
resource to enable off chip storage of security sensitive data and an internal storage resource which
automatically and irrevocably destroys plain text security sensitive data upon threat detection.
2.3.25
The MultiMediaCard (MMC), is a universal low cost data storage and communication media that is
designed to cover a wide area of applications as electronic toys, organizers, PDAs and smart phones etc.
The MMC communication is based on an advanced 7 pin serial bus designed to operate in a low voltage
range. The Secure Digital Card (SD), is an evolution of MMC technology, with two additional pins in the
form factor. It is specifically designed to meet the security, capacity, performance, and environment
requirement inherent in newly emerging audio and video consumer electronic devices. The physical form
factor, pin assignment and data transfer protocol are forward compatible with the MultiMediaCard with
some additions. Under SD, it can be categorized into Memory and I/O. The memory card invokes a
copyright protection mechanism that complies with the security of the SDMI standard. It will be faster and
provide the capability for a higher memory capacity. The I/O card provides high-speed data I/O with low
power consumption for mobile electronic devices.
The SDHC controls the MMC, SD memory, and I/O cards by sending commands to cards and performing
data accesses to/from the cards.The Multimedia Card/Secure Digital Host module (MMC/SD) integrates
both MMC support along with SD memory and I/O functions. The SDHC is fully compatible with the
MMC System Specification Version 3.0 as well as compatible with the SD Memory Card Specification
1.0, and SD I/O Specification 1.0 with 1/4 channel(s). The maximum data rate in 4-bit mode is 100 Mbps.
The SDHC uses a built-in programmable frequency counter for SDHC bus and provides a maskable
hardware interrupt for SDIO Interrupt, Internal status & FIFO status and it has a 32x16-bit data FIFO
buffer built-in.
2.3.26
The SDMA architecture offers highly-competitive DMA Controller features combined with
software-based virtual-DMA flexibility. Furthermore, it enables data transfers between peripheral I/O
devices and internal/external memories.
The Smart Direct Memory Access (SDMA) controller is a critical piece of hardware in a highly integrated
IC like a 3G Baseband chip or a Multimedia SoC. It helps maximizing system performance by off-loading
the CPU in dynamic data routing. It contains a custom RISC core along with its RAM, ROM, the three
DMA units, the CRC unit, and the scheduler.
The SDMA is used to execute short routines that perform DMA transfers; these routines or programs are
called scripts hereafter. The Instruction-Set is composed of single cycle instructions with the exception of
Load/Store instructions to the internal memory (RAM, ROM and memory mapped registers), to the
registers of the DMA and CRC units, and Branch instructions that may require several cycles to execute.
The SDMA core is interfaced to its own memory via the SDMA System Bus. The SDMA System Bus
supports a 32-bit data path and a 16-bit address bus. DMA units are interfaced to the CORE via the
Functional Unit Bus and use dedicated registers to perform DMA transfers.
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Secure Digital Host Controller (SDHC)
SDMA
i.MX31/i.MX31L Advance Information, Rev. 1.4
Preliminary
Freescale Semiconductor