MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 48

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

CSPI2_SPI_R
CSPI2_SCLK regular sw_pad_ct
DCD_DCE1
CSPI2_SS1
CSPI2_SS2
DTR_DCE1
DSR_DCE1
DTR_DTE1
DSR_DTE1
DCD_DTE1
DTR_DCE2
RI_DCE1
RI_DTE1
Pin Name
RXD1
TXD1
RTS1
CTS1
RXD2
DY
regular sw_pad_ct
regular sw_pad_ct
regular sw_pad_ct
regular sw_pad_ct
regular sw_pad_ct
regular sw_pad_ct
regular sw_pad_ct
regular sw_pad_ct
regular sw_pad_ct
regular sw_pad_ct
regular sw_pad_ct
regular sw_pad_ct
regular sw_pad_ct
regular sw_pad_ct
regular sw_pad_ct
regular sw_pad_ct
regular sw_pad_ct
Pad
l_cspi2_ss
l_cspi2_ss
l_cspi2_sc
l_cspi2_sp
l_dtr_dce1
l_dtr_dte1[
l_dsr_dte1
l_dtr_dce2
l_dcd_dce
l_dsr_dce
l_dcd_dte
l_ri_dce1
l_rxd1[0]
l_txd1[0]
l_cts1[0]
l_ri_dte1
l_rxd2[0]
l_rts1[0]
i_rdy[0]
lk[0]
1[0]
2[0]
1[0]
1[0]
1[0]
[0]
[0]
[0]
[0]
[0]
Slew Rate
0]
slow
slow
slow
slow
slow
slow
slow
slow
slow
slow
slow
slow
slow
slow
slow
slow
slow
slow
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Loopback
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
l_cspi2_ss
l_cspi2_ss
l_cspi2_sc
l_cspi2_sp
l_dtr_dce1
l_dsr_dte1
l_dtr_dce2
l_dcd_dce
l_dtr_dte1
l_dsr_dce
l_dcd_dte
l_ri_dce1
l_rxd1[2]
l_txd1[2]
l_cts1[2]
l_ri_dte1
l_rxd2[2]
l_rts1[2]
i_rdy[2]
Drive Strength
Enable (Max)
lk[2]
1[2]
2[2]
1[2]
1[2]
1[2]
[2]
[2]
[2]
[2]
[2]
[2]
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
GND sw_pad_ct
Table 6. Pad Settings (continued)
l_cspi2_sp
l_cspi2_ss
l_cspi2_ss
l_cspi2_sc
l_dtr_dce1
l_dcd_dce
l_dsr_dte1
l_dtr_dce2
l_dsr_dce
l_dtr_dte1
l_dcd_dte
l_ri_dce1
l_rxd1[1]
l_ri_dte1
l_rxd2[1]
l_txd1[1]
l_rts1[1]
l_cts1[1]
i_rdy[1]
Drive Strength
Enable0 (High/
lk[1]
1[1]
2[1]
1[1]
1[1]
1[1]
[1]
[1]
[1]
[1]
[1]
[1]
Normal)
GND pu100 pu100
GND pu100 pu100
GND pu100 pu100
GND pu100 pu100
GND pu100 pu100
GND pu100 pu100
GND pu100 pu100
GND pu100 pu100
GND pu100 pu100
GND pu100 pu100
GND pu100 pu100
GND pu100 pu100
GND pu100 pu100
GND pu100 pu100
GND pu100 pu100
GND pu100 pu100
GND pu100 pu100
GND pu100 pu100
Pull Value
pull
pull
pull
pull
pull
pull
pull
pull
pull
pull
pull
pull
pull
pull
pull
pull
pull
pull
Select
Keep
Pull/
pull sw_pad_ct
pull sw_pad_ct
pull sw_pad_ct
pull sw_pad_ct
pull sw_pad_ct
pull sw_pad_ct
pull sw_pad_ct
pull sw_pad_ct
pull sw_pad_ct
pull sw_pad_ct
pull sw_pad_ct
pull sw_pad_ct
pull sw_pad_ct
pull sw_pad_ct
pull sw_pad_ct
pull sw_pad_ct
pull sw_pad_ct
pull sw_pad_ct
l_cspi2_ss
l_cspi2_ss
l_cspi2_sc
l_cspi2_sp
l_dtr_dce1
l_dcd_dce
l_dtr_dte1[
l_dsr_dte1
l_ri_dte1[8
l_dtr_dce2
l_dsr_dce
l_ri_dce1[
l_dcd_dte
l_rxd1[8]
l_txd1[8]
l_cts1[8]
l_rxd2[8]
l_rts1[8]
i_rdy[8]
Keep Enable
lk[8]
1[8]
2[8]
1[8]
1[8]
1[8]
[8]
[8]
[8]
8]
8]
]
Pull/
VCC
VCC sw_pad_ct
VCC sw_pad_ct
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC sw_pad_ct
VCC sw_pad_ct
VCC
VCC
l_cspi2_ss
l_cspi2_sc
l_ri_dte1[3
l_dcd_dte
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
lk[3]
2[3]
1[3]
]
Open
Drain
GND
GND
GND sw_pad_ct
GND
GND
GND sw_pad_ct
GND
GND
GND
GND sw_pad_ct
GND
GND
GND
GND
GND
GND
GND
GND
l_cspi2_sc
l_dsr_dce
l_txd1[4]
Schmitt Trigger
GND
VCC
GND
GND
GND
GND
GND
GND
GND
VCC
GND
VCC
GND
GND
GND
lk[4]
1[4]
GND NVCC5
GND NVCC5
GND NVCC8
GND NVCC8
GND NVCC8
GND NVCC8
GND NVCC8
GND NVCC8
GND NVCC8
GND NVCC8
GND NVCC8
GND NVCC8
GND NVCC8
GND NVCC8
VCC NVCC5
VCC NVCC5
VCC NVCC8
VCC NVCC8
Supply
Group
Reset
Value
After
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